2018 IEEE Photonics Conference (IPC) 2018
DOI: 10.1109/ipcon.2018.8527221
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Improvement of Sidewall Roughness of Submicron SOI Waveguides by Hydrogen Plasma and Annealing

Abstract: We report the successful fabrication of low-loss submicrometric silicon-on-insulator strip waveguides for on-chip links. Postlithography treatment and postetching hydrogen annealing have been used to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line-edge roughness of 0.75 nm is obtained with the optimized process flow. As a result, record-low optical losses of less than 0.5 dB/cm are measured at 1310 nm for strip waveguide dimensions exceed… Show more

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Cited by 3 publications
(3 citation statements)
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“…The deep RIE process with a slow etching rate of 18 nm/min was performed aiming to smooth the side walls. In addition, hydrogen annealing was reported to reduce the side wall roughness [43].…”
Section: Resultsmentioning
confidence: 99%
“…The deep RIE process with a slow etching rate of 18 nm/min was performed aiming to smooth the side walls. In addition, hydrogen annealing was reported to reduce the side wall roughness [43].…”
Section: Resultsmentioning
confidence: 99%
“…a, The evolution of fully integrated photonic platforms: pure III-V platform relies on multiple epitaxial regrowths to combine active and passives structures; heterogeneous III-V on SOI requires two bonding procedures, the 'smart-cut' method to produce an integrated Si film and III-V bonding to transfer III-V epitaxy layers from native substrate onto SOI; the heterogeneous III-V on SiN platform needs only SiN direct deposition to integrate SiN film, and only one wafer bonding process to add the III-V layer. b, The spectral coverage of fully integrated PICs: boxes represent the transparency window of passive platforms on the basis of different materials (InP 52 , GaAs 53 , Si 54,55 , SiN 22,24,56 ) that can be used for fully integrated PICs, points represent the current state-of-the-art loss on these passive waveguides and wafer marker sizes represent the current maximum wafer scale in foundries. The icons on the upper side represent applications of fully integrated PICs over the spectrum map.…”
Section: Heterogeneously Integrated Iii-v On Sin Photonics Platformmentioning
confidence: 99%
“…Typical propagation losses of silicon nanowaveguides are around 2 dB/cm, which is prohibitive for scaling quantum applications. Thanks to developments in fabrication technology such as oxidization [109], [110], etchless waveguide fabrication [111], Hydrogen thermal annealing [112], and shallow waveguides [113], [60], propagation loss has been significantly reduced, with a record-low loss of 2.7 dB/m (Fig. 1f) [60].…”
Section: A Passive Componentsmentioning
confidence: 99%