Improvement of performances HfO 2 -based RRAM from elementary cell to 16 kb demonstrator by introduction of thin layer of Al 2 O 3

Azzaz, M.; Benoist, Antoine; Vianello, E.; Garbin, Daniele; Jalaguier, E.; Cagli, C.; Charpin, C.; Bernasconi, S.; Jeannot, S.; Dewolf, Tristan; Audoit, G.; Guedj, C.; Denorme, S.; Candelier, P.; Fenouillet-Béranger, C.; Perniola, L.

doi:10.1016/j.sse.2016.07.007

Cited by 21 publications

(14 citation statements)

References 14 publications

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“…Lower compliance current is found to guarantee the stable resistance states accompanied by ultra‐low RESET current (≈1 µA) and low power consumption . Moreover, with a homogeneous dispersion of defects, it is proved to reduce degradation phenomenon in HRS and ensures a high device reliability . Furthermore, due to different concentration of oxygen ions in original and additional layer, a concentration gradient is generated in the RS layer as a driving force and a modulation factor to SET voltage .…”

Section: Materials Modulationmentioning

confidence: 99%

Resistive Switching Performance Improvement via Modulating Nanoscale Conductive Filament, Involving the Application of Two‐Dimensional Layered Materials

Long

Liu

et al. 2017

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154

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Section: Materials Modulationmentioning

confidence: 99%

Resistive Switching Performance Improvement via Modulating Nanoscale Conductive Filament, Involving the Application of Two‐Dimensional Layered Materials

Long

Liu

et al. 2017

Small

154

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“…This is unlike generalpurpose processors that require N × M steps where N and M are the weight matrix's size. Recently, there has been impressive development in maturing the technology and large array sizes for PCM and OxRAMs have already been reported [49], [50]. These emerging technologies implement only positive weight (excitatory connections).…”

Section: B Neuromorphic Corementioning

confidence: 99%

“…b) Crossbar array: Although relatively large arrays of Phase Change Memory (PCM) and ReRAM devices have been already implemented [49], [50], nano-scale effects such as IR drop and electromigration may limit the crossbar size. Partitioning the larger layers into smaller memory banks and summing up the output current can be employed as a solution for scaling up RCAs [72], [73].…”

Section: Scalabilitymentioning

confidence: 99%

On-Chip Error-Triggered Learning of Multi-Layer Memristive Spiking Neural Networks

Payvand

Fouda

Kurdahi

et al. 2020

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Recent breakthroughs in neuromorphic computing show that local forms of gradient descent learning are compatible with Spiking Neural Networks (SNNs) and synaptic plasticity. Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn using gradientdescent in situ is still missing. In this paper, we propose a local, gradient-based, error-triggered learning algorithm with online ternary weight updates. The proposed algorithm enables online training of multilayer SNNs with memristive neuromorphic hardware showing a small loss in the performance compared with the state-of-the-art. We also propose a hardware architecture based on memristive crossbar arrays to perform the required vector-matrix multiplications. The necessary peripheral circuitry including presynaptic, post-synaptic and write circuits required for online training, have been designed in the subthreshold regime for power saving with a standard 180 nm CMOS process.

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“…In recent years, a large number of studies have been reported on the construction of artificial neural networks using memristor-simulated synapses [ 21 , 22 , 23 , 24 , 25 , 26 ]. However, to use a memristor array to implement a synaptic network, a memristor with high nonlinear volt-ampere characteristics [ 23 , 27 , 28 ] or a highly nonlinear selector in series [ 5 , 29 , 30 , 31 ] is required to minimize the non-idealities impact caused by potential current paths during training and inference operations.…”

Section: Introductionmentioning

confidence: 99%

The Image Identification Application with HfO2-Based Replaceable 1T1R Neural Networks

et al. 2022

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This paper mainly studies the hardware implementation of a fully connected neural network based on the 1T1R (one-transistor-one-resistor) array and its application in handwritten digital image recognition. The 1T1R arrays are prepared by connecting the memristor and nMOSFET in series, and a single-layer and a double-layer fully connected neural network are established. The recognition accuracy of 8 × 8 handwritten digital images reaches 95.19%. By randomly replacing the devices with failed devices, it is found that the stuck-off devices have little effect on the accuracy of the network, but the stuck-on devices will cause a sharp reduction of accuracy. By using the measured conductivity adjustment range and precision data of the memristor, the relationship between the recognition accuracy of the network and the number of hidden neurons is simulated. The simulation results match the experimental results. Compared with the neural network based on the precision of 32-bit floating point, the difference is lower than 1%.

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Improvement of performances HfO 2 -based RRAM from elementary cell to 16 kb demonstrator by introduction of thin layer of Al 2 O 3

Cited by 21 publications

References 14 publications

Resistive Switching Performance Improvement via Modulating Nanoscale Conductive Filament, Involving the Application of Two‐Dimensional Layered Materials

Resistive Switching Performance Improvement via Modulating Nanoscale Conductive Filament, Involving the Application of Two‐Dimensional Layered Materials

On-Chip Error-Triggered Learning of Multi-Layer Memristive Spiking Neural Networks

The Image Identification Application with HfO2-Based Replaceable 1T1R Neural Networks

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