Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric

Rahimian, Mohammad Hassan; Fathipour, Morteza

doi:10.1016/j.mssp.2016.12.011

Cited by 54 publications

(22 citation statements)

References 50 publications

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“…After investigation of the structures, RSP = 1.2 which is greater than 1 is obtained showing the superiority of the proposed structure compared with the conventional JLT device. It is worth noting that one of the basic weaknesses of the SOI‐based junctionless is related to low I ON / I OFF which can be solved by technological actions such as grading the drain doping level . As a conclusion, the reduced leakage current and high driving power are considered as key factors introducing the suggested structure as a reliable and superior candidate for conventional junctionless based on SOI technology.…”

Section: Simulation Resultsmentioning

confidence: 98%

A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

Anvarifard

2018

Int J Numerical Modelling

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Silicon-on-insulator junctionless transistor (SOI-JLT) is introduced as an efficient device for nanoscale destinations. Moreover, critical lattice temperature and high leakage current are taken into account as the fundamental challenges can limit the use of the SOI-JLTs. This paper aims to modify a conventional junctionless in order to improve the electrical and thermal performance. A new window filled by lightly doped P-type silicon material opens inside a part of the buried oxide beneath the channel region. This reformation in the junctionless creates a depletion layer at the channel region/new window interface to reduce the leakage current, successfully. Also, the critical lattice temperature of the proposed structure will be mitigated owing to higher effective thermal conduction in contrast to the conventional SOI-JLT structure. Two carriers and two-dimensional (2D) simulation of the structures under the study considering the various spectra of parameters in terms of lattice temperature, leakage current, electron temperature, driving current, transconductance, output conductance, parasitic capacitance, current gain, unilateral power gain, cutoff frequency, maximum oscillation frequency, and minimum noise figure revealed that the suggested device provides a better opportunity for the researchers and experimentalists to implement and develop it for VLSI applications.KEYWORDS depletion layer, electrical performance, junctionless, silicon-on-insulator, temperature lattice | INTRODUCTIONUtilizing the silicon-on-insulator technology is an interesting solution to improve the short channel effects and electrical performance for the nanoscale devices owing to high immunity to latch-up current, smaller parasitic capacitance, and high transconductance. 1-3 The importance of SOI technology is so high that many papers are attributed to it for both low-voltage and high-voltage cases. [4][5][6][7][8][9][10][11][12][13][14][15] The nanoscale junctionless is welcomed to VLSI industry since it overcomes the basic weaknesses of SOI-MOSFETs. The most important factor to limit using the nanoscale SOI-MOSFET structures is that they need a very sharp and step doping profile keeping the SOI technology advantages which is very hard and sometimes impossible due to technological challenges of the MOSFET-based devices. 16 The advent of the junctionless structure has given a new sprit to the VLSI industry since it is very compatible with the conventional MOSFET fabrication process along with promoted electrical performance. 17,18 It is the importance of

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Section: Simulation Resultsmentioning

confidence: 98%

A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

Anvarifard

2018

Int J Numerical Modelling

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“…This is followed by the deposition of a 3 nm thick metal layer (M 1 ) with a work-function φ 1 , using the e-beam deposition technique, as shown in Fig. 2(c) [34]. Then, a hard mask (a 4 nm thick Si layer) is deposited over the area where the M 1 /Hf O 2 stack is to be retained, as shown in Fig.…”

Section: A Device Fabricationmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this paper, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFFstate current (ION /IOF F) ratio of order ∼ 10 9. Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

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“…To avoid complex fabrication processes and high thermal budgets in TFETs, the junctionless tunneling field effect transistor (JLTFET) [22][23][24][25][26][27][28][29][30] has been studied extensively in recent years, which uses uniformly high-doping concentration in the source, channel and drain regions so that the doping concentration and type of channel region are consistent with source region and drain region. Due to uniform doping, the JLTFET is immune to random dopant fluctuations (RDFs) and overcomes complex fabrication processes in manufacturing, meanwhile, source and drain region are formed by the charge plasma concept which further avoids high thermal budgets in the JLTFET.…”

Section: Introductionmentioning

confidence: 99%

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

et al. 2019

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This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric

Cited by 54 publications

References 50 publications

A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

A nanoscale‐modified junctionless with considerable progress on the electrical and thermal issue

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

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