Improvement in electrical characteristics of Silicon on Insulator (SOI) transistor using graphene material

Karbalaei, Mohammad; Dideban, Daryoosh; Heidari, Hadi

doi:10.1016/j.rinp.2019.102806

Cited by 26 publications

(10 citation statements)

References 23 publications

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“…In the modern lives, the computing power of digital devices has been improved by the technology innovations in the miniaturisation of semiconductor transistors [ 1 ]. The famous Moore’s Law will soon experience its fundamental limit because of various constraints in bulk silicon (Si) technology, especially in the sub-10-nm atomic scales [ 2 – 4 ]. Therefore, the more-than-Moore development of the alternative field-effect transistors (FETs) has attracted much attention in the nanoelectronic research communities.…”

Section: Introductionmentioning

confidence: 99%

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

et al. 2022

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Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

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Section: Introductionmentioning

confidence: 99%

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

et al. 2022

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“…Many researchers have been proposed various SOI MOSFET formations to suppress SCEs and their related complications. [6][7][8][9][10][11][12][13] The presence of source-drain junctions on both sides of the channel remains a significant issue in SOI and FETs devices, and junctionless transistors have been suggested as a solution. [14,15] Several articles on junctionless FET (JLFET) have been presented to enhance their performance.…”

Section: Introductionmentioning

confidence: 99%

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Madadi

Orouji

2022

Physica Status Solidi (a)

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This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.

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“…For these reasons, graphene and its derivatives have become quite promising, being investigated for the production of sensors, [ 15 ] biosensors, [ 16 ] capacitors, [ 17 ] transistors, [ 18 ] batteries, [ 19 ] photovoltaic cells, [ 20 ] catalysts, [ 21 ] adsorbents for effluent treatment, [ 22 ] and as polymer reinforcement. [ 10,23 ] Among such applications, the use of these nanomaterials as a reinforcement in the production of nanocomposites has been promising as it results in materials with enhanced mechanical, electrical, barrier properties upon introduction of low filler contents allowing a wide variety of applications with a relatively low cost.…”

Section: Introductionmentioning

confidence: 99%

Interface adjustment between poly(ethylene terephthalate) and graphene oxide in order to enhance mechanical and thermal properties of nanocomposites

Souza

Pinto

Silva

et al. 2021

Polymer Engineering & Sci

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There is great interest in the use of graphene and derivatives in the production of polymer nanocomposites as it provides improvements in the properties of the materials to which they are associated. Such improvements depend heavily on filler dispersion and the interaction between the nanomaterials and the matrix. This work aimed to study the compatibility of graphene oxide (GO) with a poly(ethylene terephthalate) matrix. For this, graphite was modified using Hummers method, using reaction times of 3 and 6 h. The obtained GO was functionalized with amine, amide, and magnetite groups (FGO). The effects of the oxidation degree, functionalization and concentration of the nanofillers on the dispersion and consequently on the properties of the polymer nanocomposites were evaluated. The nanocomposites were synthesized by the solid–solid deposition method followed by the melt mixing technique. It was observed that lower concentrations of nanofiller associated with the lower degree of oxidation and functionalization improved the interaction of the nanofillers with the matrix, which resulted in better mechanical properties under tensile stresses for strain at break, maximum stress, Young's modulus and toughness. It was also observed that the glass transition and crystallization of nanocomposites increased due to a nucleating effect of the nanofillers.

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Improvement in electrical characteristics of Silicon on Insulator (SOI) transistor using graphene material

Cited by 26 publications

References 23 publications

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Interface adjustment between poly(ethylene terephthalate) and graphene oxide in order to enhance mechanical and thermal properties of nanocomposites

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