Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Flandre, Denis; Viviani, A.; Eggermont, Jean-Pierre; Gentinne, B.; Jespers, Paul

doi:10.1109/4.597291

Cited by 84 publications

(35 citation statements)

References 13 publications

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“…In this phase, the settling time reduces as increases. When the doublet moves to a higher frequency, a pair of complex conjugate poles is generated, as reported in [8] and [9]. Further increasing can push the complex conjugate pole pair up along the real axis, which continues reducing the opamps settling time.…”

Section: B Higher Order Effectsmentioning

confidence: 91%

“…When the doublet is pushed near the nondominant pole of the main opamp , [8] and [9] reported the generation of a pair of complex conjugate poles. The attempt to push this pair of poles to higher frequencies would reduce the phase margin (PM) of the circuit.…”

Section: B Higher Order Effectsmentioning

confidence: 99%

“…The unity-gain bandwidth of the opamp can easily be calculated, from (7), to be 663 MHz with the feedback factor (6) (7) If the differetial input signal sampled by C1-C2 is during the sampling phase in Fig. 7, the output voltage is given by (8), during the hold phase. In order to achieve 12-bits accuracy of the output value, the error of the output voltage should be less than half LSB.…”

Section: Gbopcad Detailsmentioning

confidence: 99%

“…On the other hand, the effort of reducing the effect of the doublet can raise a stability problem. Our work will show that the complex conjugate pole pair reported in [8] and [9] eventually pushes the system into instability. Therefore, it is necessary to optimize the design of GBO for its transient performance.…”

Section: Introductionmentioning

confidence: 99%

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GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design

Yuan

Farhat

Spiegel

2005

IEEE Trans. Circuits Syst. I

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A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. The methodology allows the optimization of the GBO in terms of ac response and settling performance and is incorporated into an automatic computer-aided design (CAD) tool, called GBOPCAD. Analytic equations and heuristics are first used by GBOPCAD to obtain a sizing solution close to the global optimum. Then, simulated annealings are used by GBOPCAD to find the global optimum. A sample opamp is designed by this tool in a 0.6-μm CMOS process. It achieves a dc gain of 80 dB, a unity-gain bandwidth of 836 MHz with 60 o phase margin and a 0.0244% settling time of 5 ns. The sample/hold front-end of a 12-bit 50-MSample/s analog-digital converter was implemented with this opamp. It achieves a signal-to-noise ratio of 81.9 dB for a 8.1-MHz input signal. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.This journal article is available at ScholarlyCommons: http://repository.upenn.edu/ese_papers/137

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Section: B Higher Order Effectsmentioning

confidence: 91%

Section: B Higher Order Effectsmentioning

confidence: 99%

Section: Gbopcad Detailsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design

Yuan

Farhat

Spiegel

2005

IEEE Trans. Circuits Syst. I

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“…The frequency response and the settling of the regulated cascode opamp were analyzed in more detail in [167] with the aid of a symbolic circuit simulator. It was found that when the doublet is pushed into higher frequencies it in fact merges with the non-dominant pole of the opamp, forming a complex pole pair and a zero.…”

Section: Gain Enhancement Techniquesmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Analysis, modelling and optimization of a gain boosted telescopic amplifier

Aloisi

Giustolisi

Palumbo

2003

Circuit Theory & Apps

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SUMMARYIn this paper, a thorough analysis of a gain-boosted telescopic ampliÿer (GBTA) is presented and a systematic design procedure for optimizing its time response will be given. Speciÿcally, the GBTA closed-loop time response will be analysed in detail and the constraints eliminating the well-known 'slow settling component' found. Subsequently, an optimization strategy based on the comparison between the GBTA time response and the time response of a pure two-pole ampliÿer (referred to as the target system) will be described. This strategy allows the designer to develop a GBTA starting from the target system speciÿcations in a simple and systematic way. The proposed procedure has been validated by means of simulations and excellent agreement found between the simulated and the expected results.

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Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Cited by 84 publications

References 13 publications

GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design

GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Analysis, modelling and optimization of a gain boosted telescopic amplifier

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