Improved sense-amplifier-based flip-flop: design and measurements

Nikolić, Borivoje; Oklobdzija, Vojin G.; Stojanović, Vladimir; Jia, Wenyan; Chiu, J.; Leung, Mkh

doi:10.1109/4.845191

Cited by 365 publications

(169 citation statements)

References 18 publications

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“…The delay of the DCDL circuit is controlled through the control bits (S i ), i.e., S 0 , S 1 , S 2 , S 3 and S"i are complementary of those control bits. The existing DCDL uses the double clocked flip-flop as a driving circuit [1], [6]. This is one of the special flip-flops which employs two different clock signals, so that it can provide different delays for LH and HL transitions.…”

Section: Existing Methodologymentioning

confidence: 99%

Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

Karpagambal¹

2015

IJRITCC

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-This paper presents a glitch free NAND based digitally controlled delay-lines for the avoidance of glitches. DCDL circuit uses control bits which can be generated using circuits called driving circuits. Different techniques of driving circuits are proposed to reduce the power consumption and the critical path delay. The proposed NAND based DCDLs have been designed in 90nm CMOS technology and it is adopted in the PLL application in order to reduce the power and delay time too. The analysis of present and proposed NAND bas ed DCDL has been represented. Simulation result shows that the circuits designed with modified DCDL reduce both the power consumption and critical path delay.

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Section: Existing Methodologymentioning

confidence: 99%

Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

Karpagambal¹

2015

IJRITCC

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“…This is because the former merely controls the discharging path while the latter needs to physically generate a pulse train. Implicit-type designs, however, face a lengthened discharging path in latch design, which leads to inferior timing characteristics [1].…”

Section: Techniques For Implementing Implicit Pulse-data Closed Tmentioning

confidence: 99%

“…In the design of sequential circuits, a major challenge is the design of an efficient D flip-flop (DFF). Several static/dynamic DFF architectures have been proposed in [1]- [10]. The topology comparison commences with the conventional single edge triggered flip-flop SET [1] typically latch data either at the positive or negative edge of the clock.…”

Section: Techniques For Implementing Implicit Pulse-data Closed Tmentioning

confidence: 99%

Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic

Jagadeeswaran¹

2012

IOSR-JVSP

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“…10. 1) Sampler: First, the incoming data is sampled with a high-speed sampler which is implemented as a Sense Amplifier based Flip-Flop [30]- [35]. The Sense Amplifier based Flip-Flop has a fast sense amplifier input with a short capture window followed by a slower regenerative latch (Fig.…”

Section: A Bb-pd and Subsamplingmentioning

confidence: 99%

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

Verbeke

Rombouts

Ramon

et al. 2018

IEEE J. Solid-State Circuits

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Abstract-Recently, there has been a strong drive to replace established analog circuits for multi-gigabit Clock and Data Recovery (CDR) by more digital solutions. We focused on PLLbased All-Digital CDR (AD-CDR) techniques which contain a Digital Loop Filter (DLF) and a Digital Controlled Oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low-complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050mm 2 and consumes only 46mW at 25Gb/s. This is the smallest area and lowest power consumption compared to the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic and supports a wide operating range (12.5Gb/s-25Gb/s), which is a significantly larger range compared to previous work. Finally, thanks to our digital architecture the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with most prior work, making our design truly adaptive.

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Improved sense-amplifier-based flip-flop: design and measurements

Cited by 365 publications

References 18 publications

Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

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