East-West Design &Amp; Test Symposium (EWDTS 2013) 2013
DOI: 10.1109/ewdts.2013.6673174
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Improved Scaling-Free CORDIC algorithm

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Cited by 3 publications
(4 citation statements)
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“…However, due to the high number of iterations and the high computational delay, it is only suitable for applications with low requirements for real-time performance [48]. In hyperbolic coordinates, assuming that after the i-th rotation, the vector (x i , y i ) rotated by an angle α i yields the vector (x i+1 , y i+1 ), the corresponding relationship between the two coordinates is as follows [49,50]:…”
Section: Dynamic Range Transformation Module Based On the Improved Sc...mentioning
confidence: 99%
“…However, due to the high number of iterations and the high computational delay, it is only suitable for applications with low requirements for real-time performance [48]. In hyperbolic coordinates, assuming that after the i-th rotation, the vector (x i , y i ) rotated by an angle α i yields the vector (x i+1 , y i+1 ), the corresponding relationship between the two coordinates is as follows [49,50]:…”
Section: Dynamic Range Transformation Module Based On the Improved Sc...mentioning
confidence: 99%
“…Nevertheless, the computation and correction of variable scale factor was a focused issue for higher radix CORDIC algorithms [ 26 , 27 , 28 , 29 ] and advanced hybrid CORDIC algorithms [ 30 ]. The scale-free CORDIC algorithm [ 31 , 32 ] approximated the sine and cosine functions by the Taylor series, thereby eliminating the need for the scalar factors, except for a limited convergence range and poor accuracy. A new hybrid CORDIC algorithm was proposed [ 33 ] to be able to further reduce the latency of CORDIC by reducing the number of iterations equal to (3 N /8) + 1.…”
Section: Related Workmentioning
confidence: 99%
“…The combination of the memory units, iterative scaling-free CORDIC algorithms, and multipliers provides a method without deformation module of the vector, which significantly saves hardware resources in FPGA implementation and reduces delays. The theoretical basis for the proposed method and its 16-bit microcontroller implementation are described in [11,14]. However, no hardware implementation on FPGA has been reported until now.…”
Section: General Approachmentioning
confidence: 99%
“…The scale factor for conventional CORDIC is √ 1 + 2 −2 and for the scaling-free CORDIC it is √ 1 + 2 −4 −2 on every iteration . An angle = 2 − is also updated by the values arctan and arctan[(2 )/(2 − 2 )] accordingly [11,14]. For a given value , influence of the scale factor on the results of calculations for the conventional CORDICs is canceled when 4], and for the scaling-free CORDIC it is canceled when √ 1 + 2 −4 −2 − 1 < Δ , beginning from [11] modul sf ≥ ⌈ − 3 4 ⌉ .…”
Section: Proposed Algorithmmentioning
confidence: 99%