Improved reliability single loop single feed 7T SRAM cell for biomedical applications

Panchal, Ashish; Sharma, Priyanka; Gupta, Aastha; Neema, Vaibhav; Tiwari, Nidhi; Sindal, Ravi

doi:10.1016/j.memori.2023.100057

Cited by 6 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Despite the larger number of transistors, careful design optimizations ensure that the area overhead remains within acceptable limits. The proposed SRAM cell demonstrates improved sensing yield and energy efficiency, with read and write energy reductions of 10%-20% compared to 6T, 8T, and 9T cells [26][27][28][29][30][31][32], while maintaining a standby power of 2.1 μW. These improvements justify the additional area required for the enhanced cell design.…”

Section: Power Analysismentioning

confidence: 99%

“…Figure 1 shows the structural configurations associated with the SNM for proposed SRAM cells compared to the conventional designs [27]. We'll describe the structure of the proposed SRAM cell in a simplified diagram format:…”

Section: Proposed Designmentioning

confidence: 99%

“…To sustain this scaling trend without compromising power efficiency, researchers explore alternative devices beyond MOSFETs [22][23][24][25][26][27][28][29][30][31]. FinFETs and Silicon nanowire FETs have emerged as promising candidates, demonstrating potential to redefine the electronics industry.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

Pal,

Upadhyaya,

Majumder

et al. 2024

Eng. Res. Express

View full text Add to dashboard Cite

In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

show abstract