2016
DOI: 10.1007/s00339-016-0530-9
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Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

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Cited by 18 publications
(5 citation statements)
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“…The asymmetric structure of the side-gate may be the main causing factor for the high gate current. Referring to the design theory of the gate engineering [21], we suppose that the initial trajectories of emission electrons can be optimized by adjusting the structural parameters. For instance, with a second gate added on the opposite side and tied electrically to the other gate, it would balance out the electric fields so that the gate interception should decrease.…”
Section: Resultsmentioning
confidence: 99%
“…The asymmetric structure of the side-gate may be the main causing factor for the high gate current. Referring to the design theory of the gate engineering [21], we suppose that the initial trajectories of emission electrons can be optimized by adjusting the structural parameters. For instance, with a second gate added on the opposite side and tied electrically to the other gate, it would balance out the electric fields so that the gate interception should decrease.…”
Section: Resultsmentioning
confidence: 99%
“…In this paper, a novel structure of the dual-material gate and Gaussian-doped source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET) is designed and investigated to enhance the performance of conventional Si-based DMG-HJLTFET [25,26]. Similar to DMG-HJLTFET, a heterostructure which narrows the tunneling barrier width between the source and channel is still adopted, and the charge plasma concept is also used for realizing a corresponding P + -I-N + structure under the assumption of n-channel JLTFETs, where polar gate (PG) uses a larger work function than control gate (CG), and PG located at the left forms the heavily doped P-type source region, while CG located at middle induces an intrinsic channel region.…”
Section: Introductionmentioning
confidence: 99%
“…In the present work, we address the tunability of sensing metrics through the optimization of gate work-function and back bias for DM p-TFET. As gate work-function and back bias both govern the extent of tunneling through the sourcechannel junction [18,19], the optimization of their values is critical for enhancing the performance of TFET biosensors. Our results demonstrate that a low value of gate work-function coupled with a back bias (opposite to the polarity of front gate voltage) should be used to enhance the sensing metrics of TFET based biosensor.…”
Section: Introductionmentioning
confidence: 99%