Improved miller capacitance of new heterostructure silicon-on-insulator tunnel FET

Chander, Sweta; Das, Rajashree; Baishya, Srimanta

doi:10.1109/tencon.2015.7373123

Cited by 2 publications

(2 citation statements)

References 11 publications

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“…Also, possible is the further scaling of the transistor [13] and thus more compact size can be acquired. In this, to boost the BTBT and enhance the Miller capacity, the oxide is overlapped with the source [14][15]. Hence, the chip's performance can be enhanced and thus HETT is one of MOSFET's best options for techniques beyond CMOS.…”

Section: Introductionmentioning

confidence: 99%

Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

Satyanarayana¹,

Prakash²

2019

IJITEE

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The battery-powered mobile devices limited energy process by MOSFET's due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET's Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT's construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.

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Section: Introductionmentioning

confidence: 99%

Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

Satyanarayana¹,

Prakash²

2019

IJITEE

View full text Add to dashboard Cite

show abstract

“…Further scaling of the transistor [13] is also possible and hence more compact size can be obtained. In this, the gate oxide is overlapped on to the source to increase the BTBT and to improve the Miller capacitance [14][15]. Therefore the performance of the chip can be improved and hence HETT is one the best alternatives of MOSFET for beyond-CMOS technologies.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

Satyanarayana¹,

Prakash²

2018

IJET

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Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.

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Improved miller capacitance of new heterostructure silicon-on-insulator tunnel FET

Cited by 2 publications

References 11 publications

Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

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