Improved Macromodeling Helps Sizing of Multi-stage Op Amps – A Case Study

Xie, Qixu; Shi, Guoyong

doi:10.21203/rs.3.rs-2311650/v1

Cited by 3 publications

(3 citation statements)

References 8 publications

(12 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Further applications to design space exploration of multistage Op Amps are addressed in a recent publication, 38 where a gm/ID‐based sampling method is further explored in depth for capturing the multiple‐target design space. We believe that the design equation based quick performance evaluation method is potentially applicable to assessing autogenerated circuit topologies as dealt with by Zhao and Zhang's work, 25 overcoming the most time‐consuming part of the synthesis work.…”

Section: Application To Autosizing With Pareto Optimizationmentioning

confidence: 99%

Automatic generation of macromodels and design equations for application to Op Amp design

Shi

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryOperational amplifier (Op Amp) is a special class of analog integrated circuits. Multiple‐stage Op Amp design is of particular interest recently. However, analysis of this class of circuits has to be done manually and requires advanced skills. Automatic analysis of this class of circuits is studied in this paper, which takes a novel approach by circuit recognition and symbolic generation. Circuit recognition is deterministic, implemented by deterministic circuit partitioning and functional block extraction methods. Symbolic analysis of extracted circuit blocks can subsequently be performed with greatly reduced complexity while generated models and equations bear more useful information for circuit design. Symbolic results so generated can be applied in design space exploration, including tasks like finding the limitation in circuit topology, conducting initial sizing, and determining performance tradeoffs. This paper proposes the key algorithms for realizing the recognition of a few well‐known functional blocks frequently used in CMOS Op Amp circuits and further explores the possibility of using the recognized circuit cells in combination with the gm/ID method for circuit sizing. Preliminary tests show that this approach is a potential candidate for locating the performance boundaries of multiple‐stage Op Amps.

show abstract

Section: Application To Autosizing With Pareto Optimizationmentioning

confidence: 99%

Automatic generation of macromodels and design equations for application to Op Amp design

Shi

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…It explores the ratio between the small-signal transconductance (g m ) of a MOSFET and the DC drain current (I D ), known as the MOSFET efficiency. The g m /I D methodology has been widely used in analog integrated circuit designs to obtain very-low-power circuits for relatively low-frequency applications [4,6,[15][16][17][18][19]. The main advantage of the methodology is that it provides a powerful sizing tool that allows the designer to take advantage of all the subthreshold regions to obtain very low power consumption circuits with very few iterations and significant time reduction in the design flow.…”

Section: Introductionmentioning

confidence: 99%

A gm/ID-Based Low-Power LNA for Ka-Band Applications

Galante-Sempere,

Torres-Clarke,

del Pino

et al. 2024

Sensors

View full text Add to dashboard Cite

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the gm/ID methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the gm/ID approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the gm/ID methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

show abstract

“…A preliminary research based on the above idea was presented in the conference paper, 23 where only a limited case study and data analytics were disclosed. This journal version has enclosed the full fundamentals and an extended justification on the multitude of aspects regarding this new methodology.…”

Section: Introductionmentioning

confidence: 99%

Multistage Op Amp design space exploration by gm/ID sampling and symbolic design equations

Xie,

Shi

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryMultiple‐stage complementary metal‐oxide‐semiconductor (CMOS) operational amplifiers (Op Amps) have been extensively studied in the literature; often, each new design reports several performance advancements over the existing ones. However, the design space boundaries of those new proposals were rarely explored. Predicting the design space boundary of a new circuit topology is usually challenging due to the dependency on many aspects of technical consideration regarding the process technology, sizing priority adopted in practice, and balancing of performance metrics on power, area, noise immunity, and so on. Knowing the design space boundary could be beneficial to a fair appraisal of new designs. In this paper, we propose a gm/ID‐based method for the design space exploration of multistage Op Amps. By introducing a sampling technique while taking advantage of the device grouping property with gm/ID, it is possible to explore the circuit performance boundary by combining approximate symbolic modeling and gm/ID table lookup. Due to the introduction of a fast performance evaluation method, a large ensemble of circuit sizing samples can be evaluated in parallel, by which an efficient data mining procedure could be incorporated to deduce the circuit samples that can achieve extremal performance at Pareto boundaries. The fidelity of this proposal has been validated via simulation program with integrated circuit emphasis (SPICE) . The sampling method is also compared with a multi‐objective genetic algorithm to show the superiority in capturing Pareto boundaries.

show abstract

Improved Macromodeling Helps Sizing of Multi-stage Op Amps – A Case Study

Cited by 3 publications

References 8 publications

Automatic generation of macromodels and design equations for application to Op Amp design

Automatic generation of macromodels and design equations for application to Op Amp design

A gm/ID-Based Low-Power LNA for Ka-Band Applications

Multistage Op Amp design space exploration by gm/ID sampling and symbolic design equations

Contact Info

Product

Resources

About