Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation

Goyal, Rohit; Shrivastava, Sachin; Parameswaran, Harindranath; Khurana, Pulkit

doi:10.1109/vlsid.2007.92

Cited by 10 publications

(2 citation statements)

References 9 publications

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“…While logic gate circuits were regarded as less sensitive to the within-die device variations than SRAM cells, the variability in logic delay has become one of the major factors that limit the voltage downscaling [3,4]. Thus, the statistical static timing analysis (statistical STA; SSTA) has been proposed for ensuring the timing margin for high-speed logic gates [7,8]. Since the STA (also SSTA) is based on the table model, featuring a high accuracy, it is not suitable for estimating circuit behaviors dependence on device parameters explicitly, which is necessary for evaluating circuit performances physically.…”

Section: Introductionmentioning

confidence: 99%

Variability Analysis of Inverter Delay Time

Aoki

Hasegawa

Itayama

et al. 2010

IEEJ Transactions Elec Engng

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The variation characteristics of the inverter delay time in a large-scale integrated (LSI) chip were evaluated by using an analytical model equation combined with the statistical simulation program with integrated circuit emphasis (SPICE) simulation as well as the experimental data obtained from a device matrix array (DMA) test vehicle [11]. We demonstrate that the variation in the two-stage delay time t d (t d = t dLH + t dHL ) is linearly proportional to the variation of the effective peak operating current of the two-stage inverter I D (7) expressed as t d /t d = − I D /I D . This remains constant whether or not the current variation was induced by the threshold voltage variation ( V th ), the current factor variation ( β), or both, even for unbalanced transistor width ratios between the p-type metal oxide semiconductor (PMOS) and the n-type metal oxide semiconductor (NMOS) (W P /W N = 0.5-5). Thus I D /I D can be regarded as a measure of the inverter delay time variation. The relative variation in the delay time increases dramatically when the supply voltage is decreased, which we attribute to the specific gate voltage dependence of the MOS drain current variation induced by the threshold voltage variation V th . 

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Section: Introductionmentioning

confidence: 99%

Variability Analysis of Inverter Delay Time

Aoki

Hasegawa

Itayama

et al. 2010

IEEJ Transactions Elec Engng

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“…Namely, when the delay d(e) of edge e from vertex v to vertex w is determined for computing the arrival time D(w) to w by adding d(e) to arrival time D (v) to v, we must use slew distribution T(v) corresponding to D(v), since D(v) and T(v) represent delay and slew of a signal propagating edge e, respectively. In [9], the slew is treated as a stochastic variable, but it considers only the case of a single path. Hence, we need a more sophisticated method to handle slews.…”

Section: Introductionmentioning

confidence: 99%

A Gaussian mixture model for statistical timing analysis

Takahashi

Yoshida

Tsukiyama

2009

Proceedings of the 46th Annual Design Automation Conference

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This paper introduces a Gaussian mixture model to represent delay and slew distributions in the statistical static timing analysis, and proposes algorithms for propagating them on a given circuit graph. The Gaussian mixture model can represent a non-Gaussian distribution due to the statistical Max operation properly, and any correlation efficiently, since it consists of plural Gaussian distributions. Therefore, not only topological correlations caused by re-convergent paths but also the correlation between each element and the critical delay, which is useful for circuit optimization, are calculated easily. The propagated slews are used to compute delay distributions of circuit elements dynamically so as to improve the accuracy. The proposed Gaussian mixture model is evaluated by comparing with Monte Carlo simulation, and the results show its effectiveness.

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Gate Delay Under Process Variations

Champac

Gervacio

2018

Timing Performance of Nanometer Digital Circuits Under Process Variations

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Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation

Cited by 10 publications

References 9 publications

Variability Analysis of Inverter Delay Time

Variability Analysis of Inverter Delay Time

A Gaussian mixture model for statistical timing analysis

Gate Delay Under Process Variations

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