Implicit state enumeration of finite state machines using BDD's

Touati, H.J.; Savoj, H.; Lin, Bill; Brayton, Robert K.; Sangiovanni‐Vincentelli, Alberto

doi:10.1109/iccad.1990.129860

Cited by 284 publications

(140 citation statements)

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“…present state variables 1 ,... n s s and input variables 1 ,... m x x ). We will assume that the conjunction is taken in the order of a bottom-up manner (i.e., Related work: The importance of the quantification schedule was first recognized by Burch et al [1] and Touati et al [2]. Geist et al [3] proposed a simple circuit independent heuristic algorithm, in which they ordered conjuncts by minimizing the maximal number of state variables of the intermediate BDDs in the processing of performing image computation.…”

Section: Preliminaries and Related Workmentioning

confidence: 99%

A genetic approach for conjunction scheduling in symbolic equivalence checking

Thornton

Szygenda

IEEE Computer Society Annual Symposium on VLSI

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Section: Preliminaries and Related Workmentioning

confidence: 99%

A genetic approach for conjunction scheduling in symbolic equivalence checking

Thornton

Szygenda

IEEE Computer Society Annual Symposium on VLSI

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“…This calls for a well-studied technique known as early quantification [27,9,14], which has been extensively used in such areas as symbolic model checking where current state variables are quantified in image computation [9]. The idea is that one should take care to perform the quantifications as early as possible, rather than all at the end, so that the intermediate BDDs will have fewer variables and a likely smaller size.…”

Section: B Variable Elimination With Bddsmentioning

confidence: 99%

MUP: a minimal unsatisfiability prover

Huang

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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Abstract-After establishing the unsatisfiability of a SAT instance encoding a typical design task, there is a practical need to identify its minimal unsatisfiable subsets, which pinpoint the reasons for the infeasibility of the design. Due to the potentially expensive computation, existing tools for the extraction of unsatisfiable subformulas do not guarantee the minimality of the results. This paper describes a practical algorithm that decides the minimal unsatisfiability of any CNF formula through BDD manipulation. This algorithm has a worse-case complexity that is exponential only in the treewidth of the CNF formula. We provide an empirical evaluation of the algorithm, highlighting its efficiency on a set of hard problems as well as its ability to work with existing subformula extraction tools to achieve optimal results.

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“…Most methods, such as symbolic model checking, use FSMs explicitly or implicitly to model the design [1,3,14]. On the other hand, most of methods use BDDs to represent Boolean functions [5,7] and there are no other suitable representations to do model checking effectively. Because of the low abstraction level BDDs, processing time of circuits represented as such becomes forbiddingly high for large circuits [7].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, most of methods use BDDs to represent Boolean functions [5,7] and there are no other suitable representations to do model checking effectively. Because of the low abstraction level BDDs, processing time of circuits represented as such becomes forbiddingly high for large circuits [7]. If we can present our model at higher abstraction levels, we will be able to verify functionality easier than in BDDs.…”

Section: Introductionmentioning

confidence: 99%