Implications of shallower memory controller transaction queues in scalable memory systems

Abstract

Scalable memory systems provide scalable bandwidth to the core growth demands in multicores and embedded systems processors. In these systems, as memory controllers (MCs) are scaled, memory traffic per MC is reduced, so transaction queues become shallower. As a consequence, there is an opportunity to explore transaction queue utilization and its impact on energy utilization. In this paper, we propose to evaluate the performance and energy-per-bit impact when reducing transaction queue sizes along with the MCs of these systems. Experimental results show that reducing 50% on the number of entries, bandwidth and energy-per-bit levels are not affected, whilst reducing aggressively of about 90%, bandwidth is similarly reduced while causing significantly higher energy-per-bit utilization.