Implementing statecharts in PROMELA/SPIN

Mikk, Erich; Lakhnech, Yassine; Siegel, Michael I.; Holzmann, Gerard J.

doi:10.1109/wift.1998.766303

Cited by 82 publications

(73 citation statements)

References 16 publications

(24 reference statements)

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“…Some of related works on connecting Statecharts with other formalisms are presented in [1,2,13,19,20,18]. Beauvais et.al.…”

Section: Discussion and Related Workmentioning

confidence: 99%

“…However, all these translations are based on the informal semantics [6] lacking correctness proofs. The authors of [2,13] transform variants of Statecharts into hierarchical timed automata and use tools (UPPAAL, SPIN) to model check Statecharts properties. Also, [20] based on the denotational semantics [9] aims to connect a subset of Statecharts with temporal logic FNLOG for theoretically proving Statecharts' properties.…”

Section: Discussion and Related Workmentioning

confidence: 99%

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Mapping Statecharts to Verilog for Hardware/Software Co-specification

Qin

Chin

2003

FME 2003: Formal Methods

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The full-text may be used and/or reproduced, and given to third parties in any format or medium, without prior permission or charge, for personal research or study, educational, or not-for-prot purposes provided that:• a full bibliographic reference is made to the original source • a link is made to the metadata record in DRO • the full-text is not changed in any way The full-text must not be sold in any format or medium without the formal permission of the copyright holders.Please consult the full DRO policy for further details. Abstract. Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics.After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

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“…Some of related works on connecting Statecharts with other formalisms are presented in [1,2,13,19,20,18]. Beauvais et.al.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Section: Discussion and Related Workmentioning

confidence: 99%

Mapping Statecharts to Verilog for Hardware/Software Co-specification

Qin

Chin

2003

FME 2003: Formal Methods

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“…The most of the proposed approaches target only activity diagrams [7,8,9,10,11] and state machine diagrams [12,13,14,15,16,17,18]. There are some approaches targeting sequence diagram and message sequence charts.…”

Section: Related Workmentioning

confidence: 99%

Automatic generation of PROMELA code from sequence diagram with imbricate combined fragments

Amirat

Menasria

Oubelli

et al. 2012

Second International Conference on the Innovative Computing Technology (INTECH 2012)

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“…Since UML is well accepted by the software industries as graphical design notations, people have been studying the formalization of UML descriptions. In particular, people have discussed various issues regarding the translation from formalized UML statechart diagrams into PROMELA [10,11,14,13].…”

Section: Related Workmentioning

confidence: 99%

Translation from Adapted UML to Promela for CORBA-Based Applications

Chen

2004

Model Checking Software

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Abstract. Nowadays, many distributed applications take advantage of the transparent distributed object systems provided by CORBA middlewares. While greatly reduce the design and coding effort, the distributed object systems may also introduce subtle faults into the applications, which on the other hand, complicate the validation of the applications. In this paper, we present our work on applying SPIN to check the correctness of the designs of CORBA-based applications, taking into account those characteristics of CORBA that are essential to the correctness of the applications. In doing so, we provide adaptations to UML, so that the CORBA-based applications can be modeled with succinct yet sufficient details of the underlying middlewares. An automated translation tool is developed to generate Promela models from such UML design models. The translation tool embeds the behavioral details of the middleware automatically. In this way, the software developers can stay in their comfort zone while design faults, including those caused by the underlying distributed object systems can be pinpointed through the verification or the simulation with SPIN.

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Implementing statecharts in PROMELA/SPIN

Cited by 82 publications

References 16 publications

Mapping Statecharts to Verilog for Hardware/Software Co-specification

Mapping Statecharts to Verilog for Hardware/Software Co-specification

Automatic generation of PROMELA code from sequence diagram with imbricate combined fragments

Translation from Adapted UML to Promela for CORBA-Based Applications

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