Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign

Dang, Viet Ba; Farahmand, Farnoud; Andrzejczak, Michał; Gaj, Kris

doi:10.1109/icfpt47387.2019.00032

Cited by 38 publications

(23 citation statements)

References 10 publications

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“…Дещо інакше, для 5-го рівня стійкості чисто апаратна реалізація NewHope, про яку повідомляється в роботі [9], недостатньо швидка для того, щоб перевершити програмно-технічну реалізацію Round5 з [10]. Однак порівняння дещо ускладнюється тим, що в [9] результати свідчать не про IND-CPA-стійке асиметричне шифрування (а не про IND-CCAстійкий КЕМ), а лише про суму генерації та розшифрування ключів (а не про саме розшифрування).…”

Section: загальні характеристики сімейства Fpga Xilinxunclassified

Research and analysis of implementations of the NIST PQC competition second round candidates focused on the Xilinx FPGA family

Yesina¹,

Shahov²

2021

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Today, the question of the stability of modern existing cryptographic mechanisms to quantum algorithms of cryptanalysis in particular and quantum computers in general is quite acute. This issue is actively discussed at the international level. Therefore, to solve it, NIST USA has decided to organize and is currently holding a competition for candidates for post-quantum cryptographic algorithms NIST PQC. The result of the competition should be the adoption of various types of cryptographic algorithms for standardization, namely, asymmetric encryption, key encapsulation and electronic signature (at least one algorithm of each type). 82 algorithms were submitted by the start of the competition for the standardization process. Based on the minimum eligibility criteria defined by NIST, 69 algorithms were considered for the 1st round. Given several parameters, namely, security, cost, performance, implementation characteristics, etc., 43 and 11 algorithms were excluded at the end of the 1st and 2nd rounds, respectively, and the other 15 algorithms were left for participation in the 3rd round. The algorithms left in the 2nd round can be divided into 5 different categories depending on their mathematical basis: those based on the isogeny of elliptic curves, those based on algebraic lattices, those based on mathematical code, those based on multivariate transformations and those based on hash functions. Security is the main evaluation criterion that determines competition in the NIST competition, and it is clear that candidates' software implementations are focused mainly on it. However, it is extremely important that the algorithm has an effective hardware implementation. Timely identification of hardware inefficiencies will help focus the cryptographic community efforts on more promising candidates, potentially saving a large amount of time that can be spent on cryptanalysis. This paper discusses and compares the FPGAs of Xilinx family. Data on the implementation of the candidates of the 2nd round in the process of standardization of post-quantum cryptography NIST, which are focused on the FPGA of the Xilinx family, are presented and compared.

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Section: загальні характеристики сімейства Fpga Xilinxunclassified

Research and analysis of implementations of the NIST PQC competition second round candidates focused on the Xilinx FPGA family

Yesina¹,

Shahov²

2021

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“…The work [33] provides hardware/software solutions for many PKE/KEM algorithms and sizes. The obtained results are interesting but cannot be compared to pure hardware ones (for instance the area required by a A53 Cortex core cannot be compared with FPGA resources).…”

Section: Comparison With Other Workmentioning

confidence: 99%

Lattice-based Cryptosystems on FPGA: Parallelization and Comparison using HLS

Zijlstra¹,

Bigou²,

Tisserand³

2021

IEEE Trans. Comput.

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This paper deals with hardware implementations for lattice-based cryptography. Various CPA and CCA secure algorithms for LWE, RLWE and MLWE problems have been studied, parallelized, implemented and compared on FPGA using high-level synthesis. The impact of PRNG choices on the implementations performances and costs is also evaluated. HLS allows us to compare various sets of algorithms, architectures and parameters with a reduced design effort. Our results are often similar to state-of-the-art for various speed and cost trade-offs. Sometimes we obtain better results thanks to the exploration of numerous architecture and algorithm optimizations.

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“…Several hardware accelerators for the lattice-based cryptography without using the NTT algorithm have been proposed recently [6], [17], [18], [31], [32], [33], [34], [35]. As expected, optimizing the polynomial multiplier is the main focus of these works, since it is the bottleneck.…”

Section: Prior Hardware Implementationsmentioning

confidence: 99%

“…As expected, optimizing the polynomial multiplier is the main focus of these works, since it is the bottleneck. The hardware/software co-design for the modular polynomial multiplication accelerator in [31] shows a significant acceleration compared with the software implementation. Subsequently, the work in [18] introduced the compact hardware/software interfacing design, which applies a hybrid method of Toom-Cook multiplication [36] (a variant of Karatsuba algorithm) and a degree-64 schoolbook polynomial multiplier to optimize the modular polynomial multiplication.…”

Section: Prior Hardware Implementationsmentioning

confidence: 99%

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography

Tan¹,

Wang²,

Lao³

et al. 2021

Preprint

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This paper presents a low-latency hardware accelerator for modular polynomial multiplication for lattice-based post-quantum cryptography and homomorphic encryption applications. The proposed novel modular polynomial multiplier exploits the fast finite impulse response (FIR) filter architecture to reduce the computational complexity for the schoolbook modular polynomial multiplication. We also extend this structure to fast M -parallel architectures while achieving low-latency, high-speed, and full hardware utilization. We comprehensively evaluate the performance of the proposed architectures under various polynomial settings as well as in the Saber scheme for post-quantum cryptography as a case study. The experimental results show that our design reduces the computational time and area-time product by 61% and 32%, respectively, compared to the state-of-the-art designs.

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Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign

Cited by 38 publications

References 10 publications

Research and analysis of implementations of the NIST PQC competition second round candidates focused on the Xilinx FPGA family

Research and analysis of implementations of the NIST PQC competition second round candidates focused on the Xilinx FPGA family

Lattice-based Cryptosystems on FPGA: Parallelization and Comparison using HLS

High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography

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