The essential purpose of this paper is to present at first an innovative theoretical modeling for the generation of pulse level detectors that can be applied for the design of A/D converters. The main goal will be to establish some intrinsic properties of the main operator introduced previously by the authors, and its intrinsic characteristics for modeling the PWM−PPM effect, and later eliminating the PWM part of the pulse stream. An idea about how to implement this technological techniques inside a modern FPGA architecture is bestowed, which makes possible for the designer obtain the Pulse Point Modulation signal at the output ports of the electronic structure.