“…Therefore, to reduce the probability of single event upset in this system, the Verilog HDL (Hardware Description Language) and the design of the peripheral circuit for the FPGA have been continuously modified and optimized. The PXIe connector is used to transmit the FPGA's output data to the NI chassis with transmission speeds that can reach up to 2.5 Gb/s [1,3,14,15,16,17,18,19]. The connection circuit diagram of FPGA and PXIe is presented in Fig.…”