Implementation Topology of Full Adder Cells

Ahmed, Rekib Uddin; Saha, Prabir

doi:10.1016/j.procs.2020.01.063

Cited by 2 publications

(2 citation statements)

References 10 publications

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“…Transistor scaling is vital to building low-power integrated circuit (IC). Transistors technologies as high-electron-mobility transistor (HEMT), heterojunction bipolar transistor (HBT), metal oxide semiconductor field effect transistor (MOSFET), and negative capacitance field effect transistor (NCFET) [4], [5] facilitate scaling to lower levels [6]. Other than typical full adder design techniques (using XOR/XNOR (or) CMOS inverters), there are some popular digital logics accessible, i.e., efficient charge recovery logic (ECRL), adiabatic logic, dual rail circuits (DRC), and reversible logic [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Daniel,

Prasad,

Chaturvedi

et al. 2024

IJRES

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<p>The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.</p>

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Section: Introductionmentioning

confidence: 99%

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Daniel,

Prasad,

Chaturvedi

et al. 2024

IJRES

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“…For intelligent system applications, complementary metaloxide-semiconductor (CMOS) design topologies of 1-bit full adder (FA) were introduced in Rekib Uddin Ahmed and Prabir Saha 2019 [9]. However, the power consumption was not minimized by CMOS design topology.…”

mentioning

confidence: 99%

Deep Neural Learning based Deming Regression Adder Enhancement on Digital Multiplier for 3D Graphical Applications in VLSI Circuits

Renuka

Valantina

2023

IJEER

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This work aims to investigate 3D Technology to provide better performance enhancement for several generations. The three-dimensional integrated circuit allows better integration density, faster on-chip communications, and heterogeneous integration. The goal of this research is to reduce time consumption and power consumption by introducing the Deep Neural Learnt Deming Regression Based Ladner-Fisher Adder Enhancement (DNLDR-LFAE) Technique in VLSI circuits. Input information (carry inputs) is taken for input layer and transmits to hidden layer 1. Deeming regression analysis has performed at hidden layer 1 to pre-process input data and it is send to hidden layer 2. In that layer, performs carry generation as well as post-processing as well as output outcomes have enclosed with convolution. Finally, at output layer, outcomes were attained to execute well-organized adder improvement of digital multiplier by lesser power as well as time consumption. DNLDR-LFAE Technique measured in terms of power, location and time consumption. An outcome of DNLDR-LFAE Technique decreases time and power consumption of adder enhancement than other methods. The hardware complexity of proposed technique obtains minimized by upto 52% to 63% when designed by Ladner-Fisher Adder.

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Implementation Topology of Full Adder Cells

Cited by 2 publications

References 10 publications

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

Deep Neural Learning based Deming Regression Adder Enhancement on Digital Multiplier for 3D Graphical Applications in VLSI Circuits

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