Implementation of Turbo decoder using MAX-LOGMAP algorithm in VHDL

Mishra, Shivshankar; Shukla, Harshit; Suneel, Madhekar

doi:10.1109/indicon.2015.7443180

Cited by 1 publication

(3 citation statements)

References 14 publications

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“…comparison with [3] that are using 4 bit data input, showing although that in this paper using number of bit twice the number of bit in the [3] and the algorithm using the robust algorithm from the [3], but the resources utilization in our work from the device is less than the [3]. Similarity in the [13] and [14]. The Log-MAP algorithm design of this paper not need to using RAM, all data is available during the processing, while in [3] and [14] using as shown 30 and 23 LUTRAM, respectively, from the devices.…”

Section: Real Time Implementation Resultsmentioning

confidence: 70%

“…Turbo code with improved Log-MAP algorithm that is implemented hardware on FPGA Kintex-7, that prove the applicable of it for real time application. Also, utilize of resources from the device is less than from previous works [3], [14], [13]. when implementation turbo decoder, there is having tradeoff between the complexity and the BER performance.…”

Section: Real Time Implementation Resultsmentioning

confidence: 99%

“…Similarity in the [13] and [14]. The Log-MAP algorithm design of this paper not need to using RAM, all data is available during the processing, while in [3] and [14] using as shown 30 and 23 LUTRAM, respectively, from the devices. Turbo code with improved Log-MAP algorithm that is implemented hardware on FPGA Kintex-7, that prove the applicable of it for real time application.…”

Section: Real Time Implementation Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Different Fpga Products Based Implementation of Lte Turbo Code

Dheeb¹,

Sabbar²

2020

Iraqi Journal of ICT

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—In the long-term evolution (LTE) physical layer, using turbo code is considered as the paramount one in error-correcting coding. This paper presents an implementation of LTE turbo decoding using the Log- Maximum a posteriori (MAP) algorithm with reduced number of required cycles approximately by 75% based on serial to parallel operation. Also an improvement for this algorithm based on polynomial regression function to reduce the implementation complexity. All this system implementation design with 40 bit block size of the input using Xilinx System Generator (XSG). This system implementation in hardware to show its applicability in real time using two approaches; Hardware Co-Simulation and HDL Netlist based on three devices, Xilinx Kintex-7, Spartan-6 and Artix-7. Observe from the hardware implementation, the system become completely real time by controlled from the user using the switches on the board. Also, this system taken the resources utilization from the devices less than other works.

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