Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

Pille, J.; Adams, Charlotte; Christensen, T.; Cottier, S.; Ehrenreich, S.; Kono, F.; Nelson, D.H.; Takahashi, Osamu; Tokito, S.; Torreiter, O.; Wagner, O.C.; Wendel, D.

doi:10.1109/jssc.2007.907999

Cited by 24 publications

(11 citation statements)

References 3 publications

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“…(5) is shown for the case where X i and Y are N (0, 1) and independent additive delays (Z i = X i + Y ). 2 Recall that failure is given by Eq. (3) and the conservative loop flattening estimate P u is defined in Eq.…”

Section: Discussionmentioning

confidence: 99%

“…This work focuses on read access yield because it has been observed in measurements that AC fails, manifested as too slow of an access time from one or more addresses, are encountered before DC failures, manifested as the corruption of data at one or more addresses [2]. Therefore, DC stability (write and read margin) is necessary but not sufficient for yielding a memory chip.…”

Section: Introductionmentioning

confidence: 99%

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Technique for Efficient Evaluation of SRAM Timing Failure

Qazi

Tikekar

Dolecek

et al. 2013

IEEE Trans. VLSI Syst.

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Abstract-This paper presents a technique to evaluate the timing variation of SRAM. Specifically, a method called loop flattening that reduces the evaluation of the timing statistics in the complex, highly structured circuit to that of a single chain of component circuits is justified. To then very quickly evaluate the timing delay of a single chain, a statistical method based on Importance Sampling augmented with targeted, high-dimensional, spherical sampling can be employed. The overall methodology has shown 650X or greater speed-up over the nominal Monte Carlo approach with 10.5% accuracy in probability. Examples based on both the large-signal and small-signal SRAM read path are discussed and a detailed comparison with state of the art accelerated statistical simulation techniques is given.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Technique for Efficient Evaluation of SRAM Timing Failure

Qazi

Tikekar

Dolecek

et al. 2013

IEEE Trans. VLSI Syst.

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“…24 Alternatively, a conservative approach to yield adds an extra off-chip power supply for the bit cells (and optionally the WLs) to improve the stability and performance yield of SRAM to the point at which the CMOS logic limits yield. 23 Finally, investigation of the dynamics of read disturbance reveal that it's possible to produce a functional memory from bit cells that exhibit failing butterfly curves under read stability. Pilo et al directly connect sense amplifiers to every BL pair so that a full-logic level is restored during a read operation.…”

Section: Nho Et Al Have Extended This Static-mentioning

confidence: 99%

Challenges and Directions for Low-Voltage SRAM

Qazi

Sinangil

Chandrakasan

2011

IEEE Des. Test. Comput.

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SRAM IS THE most common embedded-memory option for CMOS ICs. As the supply voltage of lowpower ICs decreases, it must remain compatible with the operating conditions. At the same time, increasingly parallel architectures of such low-power systems demand more on-chip cache to effectively share information across parallel processing units. Finally, supply voltage scaling improves the energy consumed by SRAM and dramatically reduces its leakage power.Achieving low-voltage operation in SRAM faces a confluence of challenges, originating from process variation, and related to bit cell stability, sensing, architecture, and efficient CAD methodologies. The trend toward increased quantity of embedded SRAM in scaled technology compounds the specific need of SRAM in low-power systems. Integrating more memory on chip provides an effective means to use silicon because of memory's lower power density, layout regularity, and performance and power benefits from reduced off-chip bandwidth. As a result, the everincreasing integration of embedded SRAM continues. 2 By employing some of the design innovations discussed in this article, this memory design minimizes energy per access and achieves a 50Â reduction in leakage power by trading off performance. Indeed, low-power systems benefit from SRAMs that function at very low voltage in the state of the art, but such design solutions of lowvoltage SRAM significantly impact area and performance. 3 Reducing this area overhead and further improving the metrics of energy per accessed bit and leakage power will enable new opportunities for low-power electronics in mobile platforms. Wearable electronics, portable medical monitors, and implantable medical devices are some of the applications requiring the storage of significant quantities of information (e.g., patient data), low-access energy caches, and a long operating lifetime from a battery.In this article, we discuss the challenges to embedded-SRAM design, with particular emphasis on the factors that limit the minimum operating supply voltage V min . We also explore various design solutions and discuss open areas of investigation. ChallengesThe workhorse of embedded memory is SRAM based on the 6T (six-transistor) cell, shown in Figure 2a. From this cell, a subarray is assembled by tiling memory cells into a grid with wordlines (WLs) running horizontally and bitlines (BLs) running vertically, as in Figure 3. Each memory cell is associated with one or more WLs and one or more BLs. Nominally, the bit cell supplies and well biases are globally connected to static voltage sources. During read, the WL voltage V WL is raised, and the memory cell discharges either BLT (bitline true) or BLC (bitline complement), depending on the stored data on nodes Q and bQ. A sense amplifier converts the differential signal to a logic-level output. Then, at the end of the read cycle, the BLs return to the positive supply rail. During write, V WL is raised and the BLs are forced to Future Landscape of Embedded MemoriesEditor's note: SRAMs capable of operating a...

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“…A powerful yet brute force solution to SRAM voltage scaling is simply not to scale, but rather to add a dedicated SRAM supply voltage higher than the standard logic supply [22]. The higher voltage as well as the offset between the two supplies can not only help to enable SRAM scaling to future technologies, but also presents a strategy to maintain SRAM functionality when logic voltages scale.…”

Section: B Low-voltage Cachesmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

Cited by 24 publications

References 3 publications

Technique for Efficient Evaluation of SRAM Timing Failure

Technique for Efficient Evaluation of SRAM Timing Failure

Challenges and Directions for Low-Voltage SRAM

Practical Strategies for Power-Efficient Computing Technologies

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