Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V

Pille, J.; Adams, Charlotte; Christensen, T.; Cottier, S.; Ehrenreich, S.; Kono, Tadahiro; Nelson, D.H.; Takahashi, Osamu; Tokito, S.; Torreiter, O.; Wagner, O.C.; Wendel, D.

doi:10.1109/isscc.2007.373424

Cited by 42 publications

(15 citation statements)

References 2 publications

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“…Compared with previously proposed suppressed WL technique [5][6][7][8][9][10][11], the proposed biasing scheme maintains a larger SNM at the read cell and covered the higher zscore range over 6.5σ, which is much higher than 4σ of conventional scheme as shown in Fig. 16.…”

Section: Snm For Read Cellmentioning

confidence: 87%

“…8). The activated WL level is VSSM (=0.7 V) same as cell "L" level which is different from the conventional one [6][7][8][9][10][11] as shown in Figs. 8 and 9.…”

Section: Elevated Cell Biasingmentioning

confidence: 92%

“…However they work effectively only within the limited conditions [5][6][7][8][9][10][11][12][13][14][15]. The WL level is suppressed by a dual-Vdd supply [5][6][7] or an internal voltage generator [8][9][10] to assist the SNM at a half-selected cell (Cell B in Fig.…”

Section: Various Trade-off Relationships Between Cell Operating Marginsmentioning

confidence: 99%

“…VSSM for memory cell array is generated from Vdd of peripheral logic. The routing for VDDM is the same as for the conventional dual-Vdd [5][6][7][8][9][10]. It is not necessary to change the layout for Vdd and Vss supplies in the peripheral logic.…”

Section: Elevated Cell Biasingmentioning

confidence: 99%

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A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

Yamauchi

2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (σVth) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to 6σ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

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Section: Snm For Read Cellmentioning

confidence: 87%

“…8). The activated WL level is VSSM (=0.7 V) same as cell "L" level which is different from the conventional one [6][7][8][9][10][11] as shown in Figs. 8 and 9.…”

Section: Elevated Cell Biasingmentioning

confidence: 92%

Section: Various Trade-off Relationships Between Cell Operating Marginsmentioning

confidence: 99%

Section: Elevated Cell Biasingmentioning

confidence: 99%

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A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

Yamauchi

2010

JSTS:Journal of Semiconductor Technology and Science

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“…The peak processing power is quoted at an impressive > 256 GFlops [75], however the corresponding power consumption is not stated, in a chart comparison with other processors [67] it is located at approximately 50W. Although lower-power versions have been released [76], [77], these presumably still have a somewhat high power consumption when considering battery powered applications.…”

Section: ) Real-time Reconfigurable Unitsmentioning

confidence: 99%

Software Defined Radio: Challenges and Opportunities

Ulversøy

2010

IEEE Commun. Surv. Tutorials

260

111

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Abstract-Software Defined Radio (SDR) may provide flexible, upgradeable and longer lifetime radio equipment for the military and for civilian wireless communications infrastructure. SDR may also provide more flexible and possibly cheaper multistandard-terminals for end users. It is also important as a convenient base technology for the future context-sensitive, adaptive and learning radio units referred to as cognitive radios. SDR also poses many challenges, however, some of them causing SDR to evolve slower than otherwise anticipated. Transceiver development challenges include size, weight and power issues such as the required computing capacity, but also SW architectural challenges such as waveform application portability. SDR has demanding implications for regulators, security organizations and business developers.Index Terms-Software defined radio, radio communication equipment, software engineering.

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