Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response

Abstract

The paper analyzes and proposes some enhancements of Ring-Oscillators-based Physical Unclonable Functions (PUFs). PUFs are used to extract a unique signature of an integrated circuit in order to authenticate a device and/or to generate a key. We show that designers of RO PUFs implemented in FPGAs need a precise control of placement and routing and an appropriate selection of ROs pairs to get independent bits in the PUF response. We provide a method to identify which comparisons are suitable when selecting pairs of ROs. Dealing with power consumption, we propose a simple improvement that reduces the consumption of the PUF published by Suh et al. in 2007 by up to 96.6%. Last but not least, we point out that ring oscillators significantly influence one another and can even be locked. This questions the reliability of the PUF and should be taken into account during the design.

Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs

“…Such performance is difficult to compensate even with error correction. However, this is not as dramatic as the results reported by (Bernard et al, 2012), who observed unreliability of 0.488 after exchanging their RO PUF control logic for another design.…”

“…Such ROs have a slower frequency, but their delays are just as prone to process variations as those with several inverters. In our designs, we are using the one-inverter variant as in (Bernard et al, 2012).…”

“…Achieving the same with Altera's Quartus software requires comparatively more effort. Bernard et al (2012) give no details of how they achieved the implementation of their RO PUF on Altera FPGAs. In Cherif, Danger, Guilley, and Bossuet (2012), another kind of delay-based PUF, called loop PUF, working with less gates than the RO PUF, is implemented for Altera FPGAs.…”

“…If an RO consists of more than 16 delaying elements, the LEs from more than one LAB must be used, which is specific to the Altera architecture. As mentioned in the introduction, Bernard et al (2012) have conducted their experiments with a constant RO length of eight LEs, giving no reason to why they chose this number.…”

“…To our knowledge, only Bernard, Fischer, Costea, and Fouquet (2012) have published results on RO PUFs with Altera FPGAs, spanning a population of 13 Cyclone II (90 nm) devices. Their contribution with regards to platform specific experiments lies in examining effects of ambient temperatures, differing voltages, and additional logic surrounding the ROs, of which 32 were implemented.…”