Implementation of Reed-Solomon CODEC for IEEE 802.16 network using VHDL code

Dayal, Priyanka; Patial, Rajeev Kumar

doi:10.1109/icroit.2014.6798383

Cited by 8 publications

(6 citation statements)

References 6 publications

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“…Several proposals of RTL architectures for RS codecs are depicted in literature. The majority of them are designed for specific applications such as wireless networks [21,22], digital television [23], and space data systems [24]. They are usually regulated by standards that specify which parametric configurations must be used in the RS codec implementation.…”

Section: Related Workmentioning

confidence: 99%

RTL development of a parameterizable Reed–Solomon Codec

Silva

Silvano

Duarte

2021

IET Computers & Digital Tech

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Error correction coding (ECC) methods have been considered essential constituents of data transmission systems. Reed–Solomon (RS) codes are a core ECC technique that have been adopted in numerous applications and standards. Several register‐transfer level (RTL) architectures for RS codecs have been proposed to address specific demands and overcome scalability challenges in speed and area. However, the influence of the main RS codec parameters on the corresponding hardware design has been undervalued by literature. The authors propose an open access intellectual property (IP) of a parameterizable RS codec and explore key aspects of its RTL development using IEEE 802.15.7 standard as illustration. Herein, it is demonstrated that formal verification has the potential to be solely used to attest the correctness of the developed IP for the RS codec configurations specified by IEEE 802.15.7. Furthermore, synthesis reports for the target field‐programmable gate array devices indicate that the proposed IP is able to cope with throughput requirements in IEEE 802.15.7.

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Section: Related Workmentioning

confidence: 99%

RTL development of a parameterizable Reed–Solomon Codec

Silva

Silvano

Duarte

2021

IET Computers & Digital Tech

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“…where, R(x) -is the received messages, T (x) -is the transmitted messages, E(x) -is the error messages. The RS decoder will identify the error messages [21]. In RS encoding, T (x) is divisible by g(x).…”

Section: Reed-solomon Codesmentioning

confidence: 99%

Investigation of error performance in OFDM with network coding techniques in multiple relay networks

Hlaing¹,

Farzamnia

Haldar

et al. 2020

Journal of Electrical Engineering

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The aim of this paper proposes an orthogonal frequency-division multiplexing (OFDM) with network coding to improve the error performance of the system when the messages are transmitted from user to receiver. Two-way relay (TWR) networks are applied to reduce the transmission time slots. The exclusive-OR (XOR) coding is used for network coding in which source nodes exchange their information via TWR nodes. The XOR coded bits provides redundancy to achieve the transmit diversity gain which improves the error performance of the TWR network. OFDM is exploited for TWR to obtain the frequency selective fading nature of wireless channels. The different modulation schemes such as Quadrature Phase Shift Keying (QPSK), 16-Quadrature Amplitude Modulation (QAM) and 64-QAM with OFDM system are simulated and QPSK is selected as it gives the lowest bit error rate (BER). The multiple relaying schemes with different numbers of the information packets are also considered in this paper. Simulation results show that multiple relay schemes provide faster transmission time and better error rate performance. Moreover, different kinds of channel coding schemes such as Convolutional, Reed-Solomon (RS) and turbo codes are applied in OFDM system with network coding to compare and evaluate the BER performance of the proposed system. From the simulation results, network coded OFDM scheme with turbo codes give better BER performance for given Signal-to-Noise Ratio (SNR) in relaying scheme with different numbers of information packets compared to those of convolutional and RS codes. It shows that, the error rate performance and transmission time is reduced 10 percent than the conventional scheme at even at low SNR value.

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“…A syndrome-based RS decoder generally consists of three main blocks: a syndrome calculation (SC) block, a key equation solver (KES) block, and a Chien search and error evaluation (CSEE) block [9]. Dayal et al [10] proposed the RS (255, 239) decoder for wireless network 802.16 introduced pipelining in Chien-Search component of decoder to improve the maximum frequency of Reed-Solomon codes. Jiang et al [11] proposed a multigigabit Reed-Solomon (RS) convolutional codes (CC) decoder architecture for 60 GHz systems.…”

Section: Related Workmentioning

confidence: 99%

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation

Kato

Choomchuay

2017

IEICE Trans. Inf. & Syst.

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This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS (255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.

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Implementation of Reed-Solomon CODEC for IEEE 802.16 network using VHDL code

Cited by 8 publications

References 6 publications

RTL development of a parameterizable Reed–Solomon Codec

RTL development of a parameterizable Reed–Solomon Codec

Investigation of error performance in OFDM with network coding techniques in multiple relay networks

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation

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