Implementation of Pipelined S-BOX Using Field Programmable Gate Array

Abstract

In this project, the Advanced Encryption Standard (AES) S-box implementation is covered in detail. An S-box is a table or function replacing input values with encrypted output values, enhancing cryptographic security. To introduce the idea of pipelining, the S-box is created using GF((2^4)^2) and the Composite Field Arithmetic (CFA) approach. Pipelining in substitution box involves processing input through stages, enhancing efficiency by overlapping operations, thereby improving throughput in cryptographic algorithms like AES. To create combinational logic, the proposed architecture uses affine mapping, Composite transformation, and Inverse Galois field arithmetic. This designed S-box model is checked for functionality and synthesized to check for resource utilization. The same design is checked for timing violations and tuned to a particular frequency. Power Analysis is performed to ensure the design will not exceed the limited power. Finally, the design is converted into a bit file to dump onto the Spartan 6 FPGA Board. This method of S-box design is better than the conventional S-box, which was based on LUT.