Implementation of Neural Networks Based ECG classifi'er on TMS320C6711 processor

Abstract

This paper presents the implementation of near numerically intensive algorithms. The internal program optimal Electrocardiogram (ECG) classifier based on Multilayer memory is structured so that a total of eight instructions can be Perceptron Neural Networks (MLP NN). In the present fetched every cycle. With a clock rate of 150MHz, the C6711 investigations the optimized MLP NN based classifier is designed and implemented for detection of normal and abnormal ECG. is capable of ng eight 32-bi instucis every Some dominant unique features of ECG are extracted using or 6.66 ns e bor indes the co71c Digital Signal Processing tools to optimize the MLP NN model. floating-point digital signal processor and a 16-bit codec For this, MLP NN network is used to maximize accuracy under AD535 for input and output. The onboard codec AD535 uses a the constraints of minimum network dimension so that its sigma-delta technology that provides analog-to-digital hardware implementation further requires minimum number of conversion and digital-to-analog conversion. A fixed sampling components to satisfy real time constraints and low power rate of 8kHz is used for the analog-to-digital converter. The consumption. The classification accuracy of MLP NN is found classifier thus designed is implemented on TMS320C6711 very good even after repeating the simulation experiments a processor based Digital Signal Processing (DSP) board [4]-number of times on different data partitions. The MLP NN thus [6].designed has been implemented on the TMS320C6711 processor.

Electrocardiogram Pattern Recognition and Analysis Based on Artificial Neural Networks and Support Vector Machines: A Review

“…While off-line systems present typically a device for ECG recording and separate software for advanced processing, realtime systems have very stringent requirements that processing speed should be as high as possible. Low-cost digital signal processors (DSP) and field programmable gate array (FPGA) have been proposed for QRS detection, feature selection and heartbeat classification based on neural networks and support vector machines [155,156]. However, a comprehensive study of this issue is outside the scope of the present review.…”