Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

Kaur, Navdeep; Patial, Rajeev Kumar

doi:10.5120/11666-7261

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A General Architecture Of Mac1

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2021

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“…The design achieved a reduction of delay by 8% for the parallel multiplier. N. Kaur and R.K. Patial [13] presented a fast 16x16 bit radix-4 modified booth multiplier using the pipeline technique. Authors have suggested the adder architecture by introducing the 3:2 compressor adders.…”

Section: A General Architecture Of Macmentioning

confidence: 99%

A Novel Approach to Develop Low Power MACs for 2D Image Filtering

Samanth

Nayak

2021

IEEE Access

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In emerging technologies, a vital role is played by ASIC designs in processor operations. There is a necessity to develop such a processor composed of low power blocks. This paper discusses the design exploration of the fixed-point multiply-accumulate unit to achieve high-speed and low power consumption. A 2D image convolution process is developed by stacking and combining several MAC blocks. The developed MAC comprises a sequential multiplier, controller, and optimized adder units. The entering image pixels and kernel pixels are checked for similarity and accordingly isolated by the controller unit, thereby saving power by eliminating the redundant multiplications. A novel idea of reducing the additions in image filtering operations is incorporated in the design. The performance of the proposed MAC showed a 28% power reduction compared to the conventional approaches.

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Section: A General Architecture Of Macmentioning

confidence: 99%