Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic

Sukhavasi, Susrutha Babu; Kalavakolanu, S R Sastry; Khan, Habibulla; Madivada, Vijaya Bhaskar

doi:10.5120/7169-9750

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2013

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“…A typical (m:n) compressor takes m equally weighted input bits and produces n-bit binary number [6]. In other words, it counts the number of 1s in the input and outputs the binary count value.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of High-Speed High-Order (n:2) and (n:3) CNFET-Based Compressors

Mehrabi¹,

Navi²,

Hashemipour³

2013

IJMO

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Abstract-Compressors, as one of the Processing Elements (PEs), are the fundamental building blocks for accumulating partial products during the multiplication process. In this paper various high speed high-order compressors such as 6:2 and 7:2 compressors are compared with 6:3 and 7:3 ones in terms of designs and hardware requirements. To evaluate their performance, they are analyzed and compared with respect to delay and Power-Delay Product (PDP). The comparison is accomplished using the recent implementation of Full-Adder cell design at transistor-level in Carbon Nanotube Field Effect Transistor (CNFET) technology. Simulations are carried out using Synopsys HSPICE with 32nm CNTFET technology and 0.65 supply voltage. The results of simulations demonstrate the superiority of the n:3structures in terms ofpropagation delay and powerconsumption around %41 and%8, respectively.

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Section: Introductionmentioning

confidence: 99%