Implementation of Low Area ALU Using Reversible Logic Formulations

Duggi, Niveditha; Rajula, Swaminadhan

doi:10.1007/978-981-33-4443-3_44

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…Multiplication is a common computer operation, but it is done on most processors, because it is time consuming and expensive [9][10][11][12][13]. There is a variety of different calculation problems that can be regulated by the speed at which they are carried out, and these are called "multiplication" [14,15].…”

Section: Introductionmentioning

confidence: 99%

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Raj

Kumar

Satyanarayana

2023

IRASE

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Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

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