Implementation of ladder diagram for programmable controller using FPGA

Miyazawa, Iko; Nagao, Takaaki; Fukagawa, M.; Itoh, Yoshiaki; Mizuya, T.; Sekiguchi, Takashi

doi:10.1109/etfa.1999.813150

Cited by 13 publications

(8 citation statements)

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“…Papers using high-level functional representations are [5]- [8], which are based on Petri nets and equivalent formulations and [9], which uses Sequential Function Charts. On the other hand, papers that work with individual PLC instructions are [10]- [11] and [2]. The first two of these papers examine only elementary boolean instructions and ignore the arithmetic operations, which are very important when dealing with demanding real world applications requiring a large number of calculations.…”

Section: Background and Related Workmentioning

confidence: 99%

FPGA implementation of PLC programs using automated high-level synthesis tools

Economakos¹,

Economakos

2008

2008 IEEE International Symposium on Industrial Electronics

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Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. In this paper we propose a fully automated design methodology for producing efficient FPGA implementations of PLC programs. The PLC programs can be prepared by automation experts using their familiar programming environments and the conversion to FPGA is done by automated high-level synthesis tools. The advantages of this approach are demonstrated on a number of standard industrial control applications.

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Section: Background and Related Workmentioning

confidence: 99%

FPGA implementation of PLC programs using automated high-level synthesis tools

Economakos¹,

Economakos

2008

2008 IEEE International Symposium on Industrial Electronics

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“…FPGA-based PLC has been generally discussed by many previous researchers [2][3][4][5][6][7][8][9][10][11][12][13]. From practical view point, it is a very valuable solution to implement FPGA-based PLC by converting ladder diagram, which is the most popular programming language, to VHDL program, which is also the most popular hardware description language for FPGA design.…”

Section: Fpga-based Plc Designmentioning

confidence: 99%

“…Step 4: Build the CSG according to (3) and finally, get a completed list array to store this graph Fig. 3c.…”

Section: The Condensed Simultaneity Graphmentioning

confidence: 99%

“…Miyazawa [2] and Ikeshita et al [3] developed a very rough manner in 1999 to convert the graphic ladder diagram into program description of very high-speed integrated circuit hardware description language (VHDL). Chen and Patyra [4] designed a VHDL model of the whole system directly from the original system requirements to build a controller.…”

Section: Introductionmentioning

confidence: 99%

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A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

Yamazaki

2009

Int J Adv Manuf Technol

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Programmable logic controller (PLC) is one of the most important components in today's manufacturing. Its performance-based microprocessor and software have been a bottleneck for improving its efficiency. To enhance the PLC performance and flexibility, a new PLC design based on field programmable gate array (FPGA) has been a hot topic because of its parallel execution mechanism and reconfigurable hardware structure. From practical viewpoint, in this paper, the authors propose an approach to implement the existing ladder diagram (LD) inside FPGA making full use of the advantage of FPGA device. The essential of this research includes two issues: (a) analyze the LD program and organize it with sequential and parallel structure and (b) implement the sequential and parallel structure of the LD program with hardware description language inside FPGA. To the first work, the condensed simultaneity graph theory is applied to optimize the LD program with sequential and parallel structure. To the second work, Boolean equations are taken as the bridge to convert the optimized LD program to the hardware description language program. Finite state machine is used to generate sensitive signals to guarantee that the performance of the converted very high-speed integrated circuit hardware description language design is the same as the original ladder diagram. A case study is practiced to verify the proposed approach in this paper.

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“…At present, no devices utilizing this fabric have been manufactured. Miyazawa et al (1999) show how Ladder Diagrams could be implemented using translation to VHDL (VHSIC Hardware Description Langugae, where VHSIC is Very High Speed Integrated Circuit). The description shows how the semantics of sequential execution could be modeled by using either clock events or instantiation of flip-flops in VHDL.…”

Section: Ladder Diagramsmentioning

confidence: 99%

FPGA Implementations of Ladder Diagrams

Bergmann

Waldeck²,

Shukla³

2013

MAS

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The performance of programmable logic controllers is often constrained by the microprocessor and the real-time firmware of the controller. Field programmable gate arrays (FPGAs) are an attractive potential implementation medium for high-speed control because of their fast and parallel execution and programmable nature. Ladder Diagrams are a standard graphical programming method for industrial controllers, but compilers from Ladder Diagrams to FPGA hardware do not yet exist. This paper explores the comparative speed of four different classes of FGPA implementation of Ladder Diagrams -Interpreted Software, Compiled Software, Interpreted Hardware and Compiled Hardware. It also explores parallel versus serial execution of Ladder Diagrams in hardware, and identifies timers as a major resource user in parallel implementations. Overall, a Shared Timer Serial Compiled Hardware system for FPGA implementation of Ladder Diagrams is recommended. Using comparable FPGA resources to other alternatives it provides a 20-600 times speed improvement over other solutions whilst maintaining correct Ladder Diagram semantics.

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Implementation of ladder diagram for programmable controller using FPGA

Cited by 13 publications

References 1 publication

FPGA implementation of PLC programs using automated high-level synthesis tools

FPGA implementation of PLC programs using automated high-level synthesis tools

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language

FPGA Implementations of Ladder Diagrams

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