Implementation of kernels on the Maestro processor

Abstract

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro pro cessor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency.On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add , FIR filter, and FFT. We measured and analyzed the performance of these kernels.The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics

“…III, Fig. 1 provides the CD, CD/W, IMB, EMB, and IOB for various existing and emerging space-grade processors in logarithmic scale, including the Honeywell HXRHPPC™ [28] and BAE Systems RAD750 ® [29], which are single-core CPUs; the Cobham GR712RC™ [30,31], Cobham GR740™ [32][33][34], and BAE Systems RAD5545™ [35], which are multicore CPUs; the Boeing Maestro™ [36][37][38], which is a many-core CPU; the Ramon Chips RC64™ [39][40][41][42][43] and BAE Systems RADSPEED™ [44,45], which are multicore DSPs; and the Xilinx Virtex-5QV FX130 [25-27,46] and Microsemi RTG4™ [47][48][49][50], which are FPGAs. Data from Fig.…”