Implementation of I&lt;sup&gt;2&lt;/sup&gt;C master bus controller on FPGA

Eswari, Bollam; Ponmagal, N.; Preethi, Kathirvel; Sreejeesh, S. G.

doi:10.1109/iccsp.2013.6577229

Cited by 2 publications

(1 citation statement)

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“…Sensing and prediction data packets are transmitted using the I 2 C protocol. The I 2 C slave is used to receive the sensing data with the front-end gateway system, and the master is used to control the back-end peripheral display and the storage devices [17], [18]. Fig.…”

Section: Edge Computing Platformmentioning

confidence: 99%

Front-End Gateway System With Serial Communication Protocol Conversion and Edge Computing Platforms

Sung,

Tung,

Huang

et al. 2023

IEEE Access

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This study presents a front-end gateway system with asynchronous and synchronous serial communication protocol conversion between the universal asynchronous receiver/transmitter (UART) protocol and inter-integrated circuit (I 2 C) protocol. The valid data and sensing data can be integrated using the I 2 C protocol and sent to an edge computing platform for automated data analysis. Our system reduces data processing time and the number of buses. The system has an edge computing platform that handles simple linear regression, base conversion, a neural network, and a text database and communicates with multiple peripheral devices. The I 2 C master and slave are constructed on the edge computing platform and implement arbitration by using the carrier-sense multiple access with collision avoidance protocol to prevent data collision. According to the results obtained from the Signal Tap logic analyzer in experiments conducted using a field-programmable gate array board, a completed 330-bit UART packet requires 755.2 s to be received, and the throughput is 436.97 kbps. By contrast, a 90-bit I 2 C packet requires 184.6 s to be received, and the throughput is 487.54 kbps. The front-end gateway sends integrated packets by using the I 2 C protocol, and the operating freuency (serial clock) of the I 2 C slave can reach up to 3.6 MHz bidirectionally. An integrated 153-bit packet requires 42.96 s to be received by the edge computing platform, and the throughput is 3.5614 Mbps, which is approximately 8.15 times higher than that of the UART packet. We also fabricated a front-end gateway ASIC by using the TSMC 90-nm 1P9M CMOS process.INDEX TERMS Serial communication protocol, universal asynchronous receiver/transmitter (UART), inter-integrated circuit (I 2 C), ZigBee, front-end gateway, edge computing platform, IoT network, application-specific integrated circuit (ASIC).

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Section: Edge Computing Platformmentioning

confidence: 99%