Implementation of I&lt;sup&gt;2&lt;/sup&gt;C master bus controller on FPGA

Eswari, Bollam; Ponmagal, N.; Preethi, K.; Sreejeesh, S. G.

doi:10.1109/iccsp.2013.6577141

Cited by 6 publications

(3 citation statements)

References 1 publication

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“…While doing so, the decreasing counter value is used as the index of the bit of the register in which the value is stored. An abstraction of this procedure is presented in (6). 6When the bit counter ran through seven cycles, the READ_DIR state is entered.…”

Section: Read_addrmentioning

confidence: 99%

Algorithmic analysis and hardware implementation of a two-wire-interface communication analyser

Schinagl

Sharp

2017

2017 Internet Technologies and Applications (ITA)

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This paper discusses the development of an algorithm for the data analysis to monitor Two-Wire-Interface operation in order to improve the reliability of communication. This algorithm is designed to improve code-efficiency with regards to hardware modelling. An algorithm for the protocol used in the Standard-Mode, Fast-Mode, Fast-Mode Plus and High-Speed-Mode was developed. The proposed algorithm has been derived using the bus protocol specification and implemented in hardware via a hardware description language. The correct operation of the algorithm was proofed by applying the hardware system on a sample communication. The paper also describes the development process of embedded systems and provides information on aspects regarding hardware modelling including a mathematical description of the TWI protocol is provided.

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Section: Read_addrmentioning

confidence: 99%

Algorithmic analysis and hardware implementation of a two-wire-interface communication analyser

Schinagl

Sharp

2017

2017 Internet Technologies and Applications (ITA)

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“…1) controller_i2c: Simulate the I 2 C serial bus communication protocol [4], for realizing the exchanging of 48-byte command.…”

Section: Hardware Designmentioning

confidence: 99%

Design of USB2.0 Data Exchanging System Based on FPGA

Qian

2014

AMM

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For achieving high-speed and large-capacity data transmission between two computers, a data exchanging system is designed. With FPGA as the data transmission medium, the exchanging of command and data is implemented through the I2C channel and Slave FIFO channel of USB2.0 chip. The system design includes both hardware and software, which are respectively realized by Verilog HDL and C++. Two computers with USB Host interfaces are connected to the development board by USB2.0 transmission line, and then exchange data directly under the control of upper computer. The simulation results show that the system is practical, reliable and easily extensible.

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“…When Philips introduced I2C in 1982, it grabbed the attention of many researchers due to its reduced interfacing hardware, especially wires [14], [15], and [16]. While a single bidirectional data line of MIMO (Master Input and Master Output) replaced both MOSI and MISO; the style of transmission starting from device address eliminated the necessity of the slave select line.…”

Section: Introductionmentioning

confidence: 99%

Area Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller

Purohit*¹,

Ahmed²

2019

IJITEE

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 Abstract: The need for miniaturization has been the driving force in chip manufacturing. The proliferation of IoT, robotics, consumer electronics and medical instruments pose unprecedented demands on the embedded system design. The area optimization can be achieved either by reducing the size of transistors or by optimizing (reducing) the circuit at the gate level. ) and slices required to build the circuit. We conclude that sophisticated optimization techniques of the circuit at the gate level has the potential to reduce the area by half. The first solution has attracted many researchers while the later has not been explored to its full potential. The aim is to design a System on Chip (SoC) to satisfy the dynamic requirements of disruptive technologies while occupying the lesser area. The design and testing of communication interfaces such as Serial Peripheral Interface (SPI), Inter-IC Communication (I2C), Universal Asynchronous Receiver and Transmitter (UART) are very crucial in the area optimization of microcontroller design. Since SPI being an important communication protocol, this work reports the preliminary research carried in the design and verification of it. In this work, Verilog is used for the design and verification of the SPI module. The results show that there is a drastic reduction in the number of Look-Up-Tables (LUTs

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Implementation of I<sup>2</sup>C master bus controller on FPGA

Cited by 6 publications

References 1 publication

Algorithmic analysis and hardware implementation of a two-wire-interface communication analyser

Algorithmic analysis and hardware implementation of a two-wire-interface communication analyser

Design of USB2.0 Data Exchanging System Based on FPGA

Area Optimization using Structural Modeling for Gate Level Implementation of SPI for Microcontroller

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