Implementation of Fractional Sample Rate Digital Down Converter for Radio Receiver Applications

Datta, Debarshi; Mitra, Partha P.; Dutta, Himadri Sekhar

doi:10.1109/devic50843.2021.9455805

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…An important part of signal processing in DDC, widely used in communication systems to adjust signal sampling rates. Digital downconversion occurs when a signal is converted from mid-band to baseband [1,2,3]. From the known DDC research topics, there is still little research work on error verification based on algorithms and hardware implementations.…”

Section: Introductionmentioning

confidence: 99%

An error verification design of DDC based on MATLAB and FPGA

Deng,

Tang

2023

Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023)

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The main work of this paper is to study the error verification problem of radar echo signal DDC algorithm implementation, and DDC has certain innovations in hardware implementation methods. The main design modules of DDC include band-pass filtering, mixing, low-pass filtering, decimation and zeroing. In the design and verification of DDC system, the time-domain dual-frequency chirp echo signal is first simulated, and the DDC processing process is verified by advanced floating-point simulation on the MATLAB platform to verify its feasibility and correctness. Then, through Verilog HDL programming, the FPGA-based DDC implementation is carried out, and the output results of each module are simulated through Medelsim. Finally, the simulation results in each FPGA module are calculated with the simulation results in MATLAB to verify the accuracy of the hardware design.

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Section: Introductionmentioning

confidence: 99%

An error verification design of DDC based on MATLAB and FPGA

Deng,

Tang

2023

Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023)

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“…Decimation is the process of decreasing the sampling rate in the digital domain using, an integer, called the decimation factor. This process has applications, in sigmadelta analog-digital-converters (SD ADC), software radio, and communications, [1], [2]. A decrease in the sampling rate introduces aliasing, which may deteriorate the decimated signal.…”

Section: Introductionmentioning

confidence: 99%

Design of Decimation Filter With Improved Magnitude Characteristic and Low Complexity

Dolecek

2022

IEEE Access

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This paper presents a novel multiplierless decimation filter with low complexity, increased aliasing rejection, and a compensated passband. Simple multiplierless filters derived from symmetric polynomials, which introduce four additional zeros into certain comb folding bands, were introduced. As a result, the comb-folding bands are wider and provide improved aliasing rejection. Polyphase decomposition is applied to move this filtering to a low rate, thus decreasing the complexity expressed in the number of adders per output sample (APOS). The improvement in the passband characteristic is achieved with the compensator, which operates at a low rate. The compensator parameters were obtained using particle swarm optimization (PSO), and presented in a signed power of two (SPT) form to obtain a multiplierless design. The compensator design provides flexibility in the trade-off between the required number of adders and the quality of compensation. The superiority of the proposed filter is verified by comparison with the methods recently proposed in the literature, regarding complexity, aliasing attenuation, and passband compensation.

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Design and Implementation of a Nearly Nyquist Polyphase Filter Structure Sampling Rate Converter for 5G Systems

Jiang,

2023

2023 5th International Academic Exchange Conference on Science and Technology Innovation (IAECST)

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Implementation of Fractional Sample Rate Digital Down Converter for Radio Receiver Applications

Cited by 4 publications

References 14 publications

An error verification design of DDC based on MATLAB and FPGA

An error verification design of DDC based on MATLAB and FPGA

Design of Decimation Filter With Improved Magnitude Characteristic and Low Complexity

Design and Implementation of a Nearly Nyquist Polyphase Filter Structure Sampling Rate Converter for 5G Systems

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