Implementation of FPGA design of FFT architecture based on CORDIC algorithm

Inguva, Sharath Chandra; Seventiline, J.B.

doi:10.1080/00207217.2020.1870750

International Journal of Electronics

2021

DOI: 10.1080/00207217.2020.1870750

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Implementation of FPGA design of FFT architecture based on CORDIC algorithm

Sharath Chandra Inguva

J.B. Seventiline

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Cited by 7 publications

(1 citation statement)

References 39 publications

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“…Telecommunications, sonar, radar, audio with video signal processing, noise cancellation are some of the applications for this filter. [6][7][8][9] The filter performance is determined by the algorithm for adaption along filter design. Passive filters attenuate the signal since the filters in the input signals frequency range.…”

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Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Immareddy,

Sundaramoorthy,

Alagarsamy

2023

ECS J. Solid State Sci. Technol.

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Finite Impulse Response (FIR) filter contributes a major role in most of the signal processing applications. However, the Finite Impulse Response filter performance is restricted by its speed, power and area usage. To address these issues, an adaptive FIR filter design using approximate adder and Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier (DA-AFIR-leadx-hybam-AC) is proposed in this manuscript for eradicating the noise in the sensor nodes. Here, Low error together with area efficient approximate adder (leadx) is used for reducing path delay and area utilization. For approximate multiplier design, proposed Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier using 15–4 Approximate Compressors (hybam-AC) is used for decreasing power consumption and design complexity. The simulation of the proposed model is implemented in Verilog and the design is synthesized in FPGA utilizing Xilinx ISE 14.5. The proposed DA-AFIR-leadx-hybam-AC filter design attains 33.6%, 22.75%, 29.69% lower power and 43.58%, 11.3%, 33.07% lower delay than the existing approaches, like DA-AFIR-MLDA-RNS, DA-AFIR-Hyb-CSD-ABR, DA-AFIR-SOPOT-MPGBP. Finally, the proposed DA-AFIR-leadx-hybam-AC filter design is applied for noise removal application in sensor nodes. The proposed Filter is implemented in MATLAB/Simulink for reading input signal.

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Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Immareddy,

Sundaramoorthy,

Alagarsamy

2023

ECS J. Solid State Sci. Technol.

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Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise

Raja,

Naveen,

Durai

et al. 2023

Analog Integr Circ Sig Process

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Distributed arithmetic-FIR filter design using Approximate Karatsuba Multiplier and VLCSA

Krishnan,

Vidhya

2024

Expert Systems with Applications

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Implementation of FPGA design of FFT architecture based on CORDIC algorithm

Cited by 7 publications

References 39 publications

Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes

Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise

Distributed arithmetic-FIR filter design using Approximate Karatsuba Multiplier and VLCSA

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