Implementation of FPGA-based level-1 tracking at CMS for the HL-LHC

Abstract

A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of 5 × 10 34 cm −2 s −1 . This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 µs, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilog are presented to show the algorithm performance in terms of data throughput and parameter resolution. ABSTRACT: A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded allsilicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of 5 × 10 34 cm −2 s −1 . This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 µs, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilog are presented to show the algorithm performance in terms of data throughput and parameter resolution.

FPGA-Based Approach to Level-1 Track Finding at CMS for the HL-LHC

“…The tracklet algorithm is implemented in firmware as eight processing steps and two transmission steps [4]:…”

“…The ever-increasing capability and the programming flexibility make FPGAs ideal for performing fast track finding. The tracklet approach allows a naturally pipelined implementation with low time multiplexing (typically a factor of [4][5][6][7][8]. It also allows for a simple emulation of the algorithm for the full detector.…”

A high-performance track fitter for use in ultra-fast electronics

“…In the online environment of these high-energy physics experiments, where high-speed electronics are used to make ultra-fast decisions about which particle collision events to store and which to reject, such sophisticated techniques can easily exceed the limits of available processing time. For example, the CMS Phase-2 upgraded level-1 trigger [4,5,6] aims to find and fit hundreds of tracks within about five microseconds after each proton-proton bunch crossing, which occur every 25 ns. Under such stringent conditions, multi-step iterative track fitting algorithms can quickly surpass the allowed time.…”

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

“…Field programmable gate arrays (FPGAs) are integrated circuits that are programmed using hardware description language. Due to their programmable and parallel nature, they have been used for event triggers in the modern experimental high energy physics field [9,10,11] extensively. FPGA based trigger algorithms generally use integer based calculations [10,12,13,14].…”

“…Due to these facts, trigger algorithms are usually developed in two software versions. One that uses floatingpoint calculations and one that uses integer calculations [10,12,13,14]. The floating-point version shows the pure algorithm performance while the integer version shows the degradation of performance due to the constraints of integer calculation and the performance of the FPGA algorithms.…”