Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs

Abstract

Abstract. Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT) processors are designed and implemented using a Xilinx Field Programmable Gate Array (FPGA) device XC 4010. This device allows a 16-point FFF/DCT processor implementation. To design the CLB-efficient FFWDCT processor in FPGAs, a pipelined bit-serial architecture with bit-parallel input data format is employed. These processors operate with a 20 MHz bit-clock and 16-bit system word length, and compute an entire 16-point DFF/DCT transform for every 16-bit clock cycle.

Digital Signal Processing with Field Programmable Gate Arrays

“…We will therefore call all algorithms that do not use a multidimensional index map, DFT algorithms, although some of them, such as the Winograd DFT algorithms, enjoy an essentially reduced computational effort. FFTs have also been developed using FPGAs for 1-D [155,156,157] and 2-D transforms [47,158]. FFTs have also been developed using FPGAs for 1-D [155,156,157] and 2-D transforms [47,158].…”

Architecutres, Models, Algorithms, and Software Tools for Configurable Computing

“…Each model consists of 16 randomly generated feature points in 2 dimensions. This results in a hash table having 4 x 2 20 entries. These feature points were generated according to a Gaussian distribution with zero mean and unit standard deviation as in [16,18].…”

“…Based on a control bit pattern the switch performs rotate-shift on the input bit pattern. It has been proved that that the REBSIS model is more powerful than several word models [20] but the Bit Model [13] of reconfigurable mesh has been shown to be able to simulate the REBSIS model using the same area.…”

“…This ability of the reconfigurable mesh model to allow single cycle reconfiguration, arbitrary IN topologies, and use of local data to determine configuration has led to the development of several efficient algorithms. Examples include sorting N numbers, multiplying two N bit numbers and NxN matrix multiplication all in 0(1) time onanA^xJV reconfigurable mesh [15,20]. Efficient algorithms for this model of computation have been found for problems such as maze routing, Voronoi diagrams, histogram computation [10,19].…”

“…In the reconfigurable buses with shift switching (REBSIS) [20] model, each word level switch consists of several bit level switches. In each connection pattern each of the bit level switches share a common connection pattern to control the bit level buses in a uniform way.…”