Implementation of Elliptic Curve Cryptography over a Server-Clie|nt network

B, Bore Gowda S

doi:10.1109/icdcs48716.2020.243562

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…Radio-frequency identification networks (RFID) [9], [10], [11], internet-of-things (IoTs) [12], [13], [14], [15] and wireless sensor nodes (WSNs) [16] are typical examples of area-constrained cryptographic applications that demand low complexity H/W realization of the ECC's PM computation. Instead of these applications, other related applications are error correction codes [17], digital signal processors [18], network servers [19], etc.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Elliptic-Curve Point Multiplication Over GF(2²³³) Using Booth Polynomial Multiplier for Area-Sensitive Applications

Aljaedi,

Qureshi,

Hazzazi

et al. 2024

IEEE Access

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This article presents an area-efficient hardware architecture for the implementation of ellipticcurve point multiplication (PM) operation over GF (2 233 ). The area is minimized through three strategies: (i) implementing a bit-serial-based Booth polynomial multiplication architecture to multiply two polynomials with clock cycles overhead, (ii) using one modular adder, Booth multiplier and square block in the arithmetic unit, and (iii) realizing the modular inversion computation using the implemented square and Booth multiplier circuits. Moreover, the critical path is evaluated by the placement of registers in the datapath of the PM and Booth multiplier architectures. Moreover, a dedicated finite-state machine is implemented for control functionalities. Finally, a figure-of-merit (FoM), defined as throughput/area, facilitates realistic comparisons. The implementation results are reported on Xilinx field-programmable gate array (FPGA) devices. On the Virtex-7 device, our accelerator utilizes 1343 slices and can operate on a maximum of 393M Hz, requiring 174457 clock cycles and 443.91µs for one PM computation. It consumes 1361mW power. The implementation results and comparison to state-of-the-art show that the proposed accelerator is suitable for cryptographic applications that demand lower hardware resource utilization without significant concerns regarding computation time.

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