Implementation of Deep Learning Models on an SoC-FPGA Device for Real-Time Music Genre Classification

Abstract

Deep neutral networks (DNNs) are complex machine learning models designed for decision-making tasks with high accuracy. However, DNNs require high computational power and memory, which limits such models to fitting on edge devices, resulting in unnecessary processing delays and high energy consumption. Graphical processing units (GPUs) offer reliable hardware acceleration, but their bulky sizes prevent their utilization in portable equipment. System-on-chip field programmable gated arrays (SoC-FPGAs) provide considerable computational power with low energy consumption, making them ideal for edge computing applications, owing to their innovative, flexible, and small design. In this paper, we implement a deep-learning-based music genre classification system on a SoC-FPGA board, evaluate the model’s performance, and provide a comparative analysis across different platforms. Specifically, we compare the performance of long short-term memory (LSTM), convolutional neural networks (CNNs), and a hybrid model (CNN-LSTM) on an Intel Core i7-8550U by Intel Cooperation. The models are fed an acoustic feature called the Mel-frequency cepstral coefficient (MFCC) for training and testing (inference). Then, by using the advanced Vitis AI tool, a deployable version of the model is generated. The experimental results show that the execution speed is increased by 80%, and the throughput rises four times when the CNN-based music genre classification system is implemented on SoC-FPGA.

Reliable Multimodal Heartbeat Classification using Deep Neural Networks

“…Deep learning models such as CNNs [12]- [15], recursive neural networks (RNNs) [16], long short-term memory networks (LSTMs) [17], autoencoders [18], and hybrid models combining CNN and LSTM architectures [19]- [21] have been frequently used in the literature for arrhythmia classification. CNNs have emerged as promising networks for ECG arrhythmia classification, primarily due to their ability to handle multidimensional signals and images effectively.…”

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset

“…In recent years, there has been a rapid development in deep neural networks (DNNs), and the implementation of DNN accelerators on Field Programmable Gate Arrays (FPGAs) has gained popularity due to their advantages, such as low power consumption, high integration, and flexibility [1][2][3][4][5][6]. At the same time, machine learning on advanced allprogrammable multiprocessor systems on chips (MPSoCs) has also gained traction [7][8][9][10][11][12]. Vendors like AMD/Xilinx have released white papers on DNN implementation with INT4 optimization on Zynq UltraScale+ MPSoC and Zynq-7000 SoC [7].…”

“…Numerous studies have explored neural network implementation on advanced MP-SoCs using various models and techniques [10][11][12][13][14][15][16][17][18][19][20]. However, these MPSoCs, which are manufactured with scaled technology, such as the 16nm FinFET technology, are susceptible to single event upsets (SEUs) in irradiative environments.…”

“…Effort design recognition accuracy enhancement. II: the neurons of each hidden layer are31,31,31,31,10).…”