Implementation of Data-optimized FPGA-based Accelerator for Convolutional Neural Network

Cho, Mannhee; Kim, Young‐Min

doi:10.1109/iceic49074.2020.9050993

Cited by 14 publications

(5 citation statements)

References 4 publications

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“…Moreover, for a fair comparison, the proposed accelerator is compared with the other LeNet CNN implementations in the literature having the same number of convolutional and fully connected layers [17] [24] [25]. The design of [24] is using Zynq Ultrascale FPGA and HLS is used in the development stage. In the design of [25], a ZCU102 board with a Xilinx FPGA chip ZU9EG is used and different accelerators are used for processing the CNN layers.…”

Section: Discussionmentioning

confidence: 99%

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation

Irmak

Alachiotis

Ziener

2021

2021 29th Signal Processing and Communications Applications Conference (SIU)

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Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.

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Section: Discussionmentioning

confidence: 99%

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation

Irmak

Alachiotis

Ziener

2021

2021 29th Signal Processing and Communications Applications Conference (SIU)

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“…Several studies [19][20][21] have investigated hardware accelerators for MNIST classification using neural networks, primarily centered on CNNs. These studies also provide comparisons of speed and resource utilization in contrast to CPUs or GPUs.…”

Section: Related Workmentioning

confidence: 99%

FPGA Implementation of Complex-Valued Neural Network for Polar-Represented Image Classification

Ahmad,

Zhang,

Chowdhury

2024

Sensors

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This proposed research explores a novel approach to image classification by deploying a complex-valued neural network (CVNN) on a Field-Programmable Gate Array (FPGA), specifically for classifying 2D images transformed into polar form. The aim of this research is to address the limitations of existing neural network models in terms of energy and resource efficiency, by exploring the potential of FPGA-based hardware acceleration in conjunction with advanced neural network architectures like CVNNs. The methodological innovation of this research lies in the Cartesian to polar transformation of 2D images, effectively reducing the input data volume required for neural network processing. Subsequent efforts focused on constructing a CVNN model optimized for FPGA implementation, emphasizing the enhancement of computational efficiency and overall performance. The experimental findings provide empirical evidence supporting the efficacy of the image classification system developed in this study. One of the developed models, CVNN_128, achieves an accuracy of 88.3% with an inference time of just 1.6 ms and a power consumption of 4.66 mW for the classification of the MNIST test dataset, which consists of 10,000 frames. While there is a slight concession in accuracy compared to recent FPGA implementations that achieve 94.43%, our model significantly excels in classification speed and power efficiency—surpassing existing models by more than a factor of 100. In conclusion, this paper demonstrates the substantial advantages of the FPGA implementation of CVNNs for image classification tasks, particularly in scenarios where speed, resource, and power consumption are critical.

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“…The overall latency of the design on a Cyclone IVE FPGA is about 2.2 s. Additionally, hardware design engines have been widely employed as accelerators for complex computations of neural networks. For example, a latency of 3.58 ms and 3.2 ms with an accuracy of 98.64% and 96% were achieved in two high-level synthesis designs on LeNet-5 CNN, presented in [ 21 , 22 ], respectively.…”

Section: Related Workmentioning

confidence: 99%

Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language

2023

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This paper presents a parameterizable design generator on convolutional neural networks (CNNs) using the Chisel hardware construction language (HCL). By parameterizing structural designs such as the streaming width, pooling layer type, and floating point precision, multiple register–transfer level (RTL) implementations can be created to meet various accuracy and hardware cost requirements. The evaluation is based on generated RTL designs including 16-bit, 32-bit, 64-bit, and 128-bit implementations on field-programmable gate arrays (FPGAs). The experimental results show that the 32-bit design achieves optimal hardware performance when setting the same weights for estimating the quality of the results, FPGA slice count, and power dissipation. Although the focus is on CNNs, the approach can be extended to other neural network models for efficient RTL design.

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Implementation of Data-optimized FPGA-based Accelerator for Convolutional Neural Network

Cited by 14 publications

References 4 publications

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation

FPGA Implementation of Complex-Valued Neural Network for Polar-Represented Image Classification

Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language

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