Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation

Rajput, Anil; Pattanaik, Manisha

doi:10.1109/incet49848.2020.9154137

Cited by 22 publications

(13 citation statements)

References 8 publications

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“…The RWL[0] and RWL [1] are enabled to perform the IMBC operations (NAND, AND, OR, NOR, XOR) on operands A and B. The resulting voltage at RBL (VRBL) depends on the operand value store in the bit-cell [21], [22]. The resulting voltage of RBL is compared to VREF 1 by using SA2.…”

Section: A Imbc In 7t2m Nvsrammentioning

confidence: 99%

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2022

IJERECE

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The current computing systems are facing von Neumann bottleneck (VNB) in modern times due to the high prominence on big-data applications such as artificial intelligence and neuromorphic computing. In-memory computation is one of the emerging computing paradigms to mitigate this VNB. In this paper, a memristor-based robust 7T2M Nonvolatile-SRAM (NvSRAM) is proposed for energy-efficient In-memory computation. The 7T2M NvSRAM is designed using CMOS and memristor with a higher resistance ratio, which improved the write margin by 74.44% and the energy consumption for read and write operation by 5.10% and 9.66% over conventional 6T SRAM at the cost of increment in write delay. The read decoupled path with the VGND line enhances the read margin and read path Ion/Ioff ratio of 7T2M NvSRAM cell by 2.69× and 102.42%, respectively over conventional 6T SRAM. The proposed cell uses a stacking transistor to reduce the leakage power in standby mode by 64.20% over conventional 6T SRAM. In addition to the normal SRAM function, the proposed 7T2M NvSRAM performs In-Memory Boolean Computation (IMBC) operations such as NAND, AND, NOR, OR, and XOR in a single cycle without compute-disturb (stored data flips during IMC). It achieves 4.29-fJ/bit average energy consumption at 1.8 V for IMBC operations.

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Section: A Imbc In 7t2m Nvsrammentioning

confidence: 99%

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2022

IJERECE

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“…Many approaches to Logic-In-Memory can be found in literature; however, two main approaches can be distinguished. The first one can be classified as Near-Memory Computing (NMC) [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], since the memory inner array is not modified and logic circuits are added at the periphery of this; the second one can be denoted as Logic-in-Memory (LiM) [19][20][21][22][23][24][25][26][27][28], since the memory cell is directly modified by adding logic circuits to it.…”

Section: Introductionmentioning

confidence: 99%

“…Many applications can benefit from the IMC approach, such as machine learning and deep learning algorithms [4,6,[8][9][10][11][12]14,15,19,[21][22][23][24], but also general purpose algorithms [2,5,7,13,[16][17][18]20,25,26]. For instance: in [19], a 6T SRAM cell is modified by adding two transistors and a capacitor to it, in order to perform analog computing on the whole memory, which allows to implement approximated arithmetic operations for machine learning algorithms; in [18], logic layers consisting of latches and LUTs are interleaved with memory ones in an SRAM array, in order to perform different kinds of logic operations directly inside the array; in [26], the pass transistors of the 6T SRAM cell are modified to perform logic operations directly in the cell, which allows the memory to function as an SRAM, a CAM (Content Addressable Memory) or a LiM architecture.…”

Section: Introductionmentioning

confidence: 99%

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

et al. 2021

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The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories.

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“…However, the proposed scheme suffered from compute-failure(provides false computing results) due to process variations [12]. The author in [13] has presented the sensing scheme to overcome the compute-failure in 8T SRAM for IMC operation. Apart from this, the author in [14] has used the separate write word line to perform compound Boolean logic with searching operations with the help of 8T SRAM.…”

mentioning

confidence: 99%

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

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The In-Memory Computing (IMC) architecture based on 6T, 8T, 10T SRAM fails under process-variation and suffers from compute-disturb, compute-failure, half-select issue, respectively, which affect the reliability of IMC operation. To overcome these problems, local bit-line sharing Dual-Port 8T (SDP8T) SRAM with Virtual VSS is proposed to improve the stability and energy efficiency of IMC architecture. The decouple read-write path with high-Vth transistor is used to improve the read-margin by 2.11× and reduce the read-energy by 36.35% as compared to Transpose-8T SRAM. The virtual VSS write assist is used in SDP8T SRAM to improve the write-margin by 26.49%, and lower the leakage power by 47.95% as compared to Transpose-8T SRAM. Furthermore, IMC architecture is proposed using SDP8T SRAM. In addition to the SRAM function, SDP8T-IMC architecture performs In-memory Boolean computation(IMBC) operations without compute-disturbance and compute-failure. The remarkable feature of SDP8T-IMC architecture is that it performs IMBC operation on four operands simultaneously using all four bit-line ports in a single cycle, thus doubling the throughput and obtain 11.04 fJ/bit average energy consumption at 1 V supply. The maximum operating frequency of the proposed IMC architecture is 1050 MHz at 1 V. Cumulatively, the proposed SDP8T-IMC architecture has 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05%, and 65.28% reduction in energy consumption as compared to C6T, 6TCSRAM, 8+T, 8T, 10T, 12T, and 4+2T SRAM based IMC architectures, respectively. Moreover, the proposed IMC architecture is configured as Binary Content Addressable Memory (BCAM) for searching applications which achieves 0.60fJ energy consumption per search/bit at 1 V.

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Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation

Cited by 22 publications

References 8 publications

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Untitled

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

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