Implementation of binary edwards curves for very-constrained devices

Koçabas, Ünal; Fan, Junfeng; Verbauwhede, Ingrid

doi:10.1109/asap.2010.5541003

Cited by 28 publications

(46 citation statements)

References 21 publications

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“…In Table V, the proposed BEC FPGA implementation is compared with BEC processor implementation on ASIC [12,13].ln the proposed work, the design of the FPGA based BEC processor is explained and a comparison of the design is made with existing BEC processors and ECC processor. Since, our implementation is over FPGA platform, large numbers of registers are used to obtain a faster design.…”

Section: Implementation Results and Discussionmentioning

confidence: 99%

Fast computation of scalar multiplication over Binary Edwards Curve processor against side channel attack

Venkatasubramani¹,

Kumar²,

Vignesh³

et al. 2014

2014 International Conference on Electronics and Communication Systems (ICECS)

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Effective implementation of scalar multiplication is vital for Elliptic Curve Crypto-Processor over GF (2m). They have problems in terms of unified ness and completeness that is overcome by the Edwards Curve. In this paper, the scalar multiplication is done using Non Adjacent Form Algorithm (NAF). We illustrate parallelization in group operation level by utilizing unified addition formulas computation for Binary Edwards Curve (BEC). This decreases the number of field arithmetic operations, specifically multiplications, in the critical path by using many multipliers simultaneously. Also there is significant reduction in number of clock cycles and register resource at the expense of area usage. We estimate the LUT com p lexity and tradeoffs between time-area of the proposed BEC processor on FPGA. The results prove that the proposed BEC processor has better time performance compared to existing techniques.

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Section: Implementation Results and Discussionmentioning

confidence: 99%

Fast computation of scalar multiplication over Binary Edwards Curve processor against side channel attack

Venkatasubramani¹,

Kumar²,

Vignesh³

et al. 2014

2014 International Conference on Electronics and Communication Systems (ICECS)

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“…The estimated total number of NAND gates equivalent (GE) is 12,102 from the synthesized results, and a maximum clock frequency is 800 MHz. However, we use a clock frequency of 1,130 KHz in order to compare with other works [15][16][17]. As can be seen, the proposed architecture uses a similar number of NAND gates compared to other works.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…As can be seen, the proposed architecture uses a similar number of NAND gates compared to other works. However, the proposed architecture requires only 52,012 clock cycles, which is a half, a quarter, and onefifth of that in [15][16][17], respectively, to finish one point multiplication. Furthermore, at a clock frequency of 1,130 KHz used in Lee et al [17], the proposed architecture finishes a point multiplication after 46 ms.…”

Section: Results and Comparisonmentioning

confidence: 99%

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

Tan¹,

Lee

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

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“…El parámetro d cumple con una serie de condiciones [6] y se opera como una palabra de 251 bits, en un arreglo de 8 longs.…”

Section: Aritmética De Curvas De Edwards Binariasunclassified

“…En el año 2010 Unal Kocabas, J. Fan y I. Verbauwhethe, presentaron una implementación en hardware de curvas de Edward Binarias [6].…”

Section: Introductionunclassified

Implementation of addition and doubled of a point on a curve in a field Edwards binary // Implementación de suma y doblado de un punto en una curva de Edwards en un campo binario

2017

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RESUMENEn este artículo se presentan los resultados del diseño y desarrollo de operaciones de la aritmética de curvas de Edwards en el campo de Galois GF (2251). Se implementaron las operaciones de suma y doblado de puntos en una curva de Edwards binaria basado en la aritmética de campo finito utilizando una base polinomial. La evaluación de las operaciones se realizó sobre un sistema multiprocesador MPSoC, utilizando las capacidades de multiprocesamiento. En las operaciones de la aritmética en curvas de Edward y campos finitos se utilizan algoritmos eficientes y adecuados para un sistema de multiprocesamiento MPSoC Propeller.Palabras clave: MPSoC; Propeller; Aritmética de curvas de Edwards; Aritmética de campos finitos, Curva binaria de Edwards. ABSTRACTThis article presents the results of the design and development of operations of arithmetic of curves of Edwards in the field of Galois GF (2251). Is implemented the operations of sum and bent of points in a curve of Edwards binary based on the arithmetic of field finite using a base polynomial. The operations were evaluated on a system multiprocessor MPSoC, using multiprocessing capabilities. Operations of arithmetic in finite fields and Edward curves are used in appropriate and efficient algorithms for a multiprocessing system MPSoC Propeller.

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Implementation of binary edwards curves for very-constrained devices

Cited by 28 publications

References 21 publications

Fast computation of scalar multiplication over Binary Edwards Curve processor against side channel attack

Fast computation of scalar multiplication over Binary Edwards Curve processor against side channel attack

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

Implementation of addition and doubled of a point on a curve in a field Edwards binary // Implementación de suma y doblado de un punto en una curva de Edwards en un campo binario

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