Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

Nawathe, Umesh; Hassan, Mahmudul; Yen, King C.; Kumar, Ashok; Ramachandran, Aparna; Greenhill, D.

doi:10.1109/jssc.2007.910967

Cited by 76 publications

(34 citation statements)

References 8 publications

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“…Each L1 cache is shared among the 8 hardware threads of a core and is writethrough to the LLC. The 8 cores communicate with the shared LLC through a crossbar [36], which means that each core is equidistant from the LLC (uniform). The cache-coherence implementation is directory-based and uses duplicate tags [32], i.e., the LLC cache holds a directory of all the L1 lines.…”

Section: Single-socket -Uniform: Niagaramentioning

confidence: 99%

Everything you always wanted to know about synchronization but were afraid to ask

David

Guerraoui

Trigonakis

2013

Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles

197

126

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This paper presents the most exhaustive study of synchronization to date. We span multiple layers, from hardware cache-coherence protocols up to high-level concurrent software. We do so on different types of architectures, from single-socket -uniform and nonuniform -to multi-socket -directory and broadcastbased -many-cores. We draw a set of observations that, roughly speaking, imply that scalability of synchronization is mainly a property of the hardware.

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Section: Single-socket -Uniform: Niagaramentioning

confidence: 99%

Everything you always wanted to know about synchronization but were afraid to ask

David

Guerraoui

Trigonakis

2013

Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles

197

126

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“…The best known representatives of this class are GPU architectures from NVIDIA and AMD, which are now increasingly used for general-purpose computation that offer abundant parallelism and can be effectively mapped to these GPUs. Other examples include the Sun Niagara 2 [24] and the upcoming Intel Many Integrated Core (MIC) architecture. Research machines such as UT Austin's TRIPS [9], MIT's RAW [28] (available commercially as the TILE architecture from Tilera [2]), and UMD's XMT [33,36] are also examples of single-chip many-cores.…”

Section: Fig 1 Miss Handling Architecture (Mha) For a Banked Cache mentioning

confidence: 99%

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

Caragea

Tzannes

Keceli

et al. 2011

Int J Parallel Prog

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Abstract. Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi-and many-cores with shared parallel caches further increase MLP demand. Current cache hierarchies however have been unable to keep up with this trend, with modern designs allowing only 4-16 concurrent cache misses. This disconnect is exacerbated by recent highly parallel architectures (e.g. GPUs) where power and area per-core budget favor numerous lighter cores with less resources, further reducing support for MLP on a per-core basis. Support for hardware and software prefetch increases MLP pressure since these techniques overlap multiple memory requests with existing computation. In this paper, we propose and evaluate a novel Resource-Aware Prefetching (RAP) compiler algorithm that is aware of the number of simultaneous prefetches supported, and optimized for the same. We implemented our algorithm in a GCC-derived compiler and evaluated its performance using an emerging fine-grained many-core architecture. Our results show that the RAP algorithm outperforms a well-known loop prefetching algorithm by up to 40.15% in run-time on average across benchmarks and the state-of-the art GCC implementation by up to 34.79%, depending upon hardware configuration. Moreover, we compare the RAP algorithm with a simple hardware prefetching mechanism, and show run-time improvements of up to 24.61%. To demonstrate the robustness of our approach, we conduct a designspace exploration (DSE) for the considered target architecture by varying (i) the amount of chip resources designated for per-core prefetch storage and (ii) off-chip bandwidth. We show that the RAP algorithm is robust in that it improves performance across all design points considered. We also identify the Pareto-optimal hardware-software configuration which delivers 53.66% run-time improvement on average while using only 5.47% more chip area than the bare-bones design.

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“…Examples of homogenous multicore processors include IBM's POWER6 dual-core multithreaded processors [16], [17], AMD's quad-core Opteron processors [18], Intel's dual-core and quad-core Xeon processors [19], [20], Compaq's Piranha 8-core research prototype processor, and Sun Microsystems' T1 and T2 8-core multithreaded processors [21], [22]. An overview of early homogenous multicore designs is presented in [23].…”

Section: Chmmentioning

confidence: 99%

Capacity metric for chip heterogeneous multiprocessors

Otoom

Paul

2011

Proceedings of the Seventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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The primary contribution of this thesis is the development of a new performance metric, Capacity, which evaluates the performance of Chip Heterogeneous Multiprocessors (CHMs) that process multiple heterogeneous channels. Performance metrics are required in order to evaluate any system, including computer systems. A lack of appropriate metrics can lead to ambiguous or incorrect results, something discovered while developing the secondary contribution of this thesis, that of workload modes for CHMsor Workload Specific Processors (WSPs).For many decades, computer architects and designers have focused on techniques that reduce latency and increase throughput. The change in modern computer systems built around CHMs that process multi-channel communications in the service of single users calls this focus into question. Modern computer systems are expected to integrate tens to hundreds of processor cores onto single chips, often used in the service of single users, potentially as a way to access the Internet. Here, the design goal is to integrate as much functionality as possible during a given time window. Without the ability to correctly identify optimal designs, not only will the best performing designs not be found, but resources will be wasted and there will be a lack of insight to what leads to better performing designs. To address performance evaluation challenges of the next generation of computer systems, such as multicore computers inside of cell phones, we found that a structurally different metric is needed and proceeded to develop such a metric.In contrast to single-valued metrics, Capacity is a surface with dimensionality related to the number of input streams, or channels, processed by the CHM. We develop some fundamental Capacity curves in two dimensions and show how Capacity shapes reveal interaction of not only programs and data, but the interaction of multiple data streams as they compete for access to resources on a CHM as well. For the analysis of Capacity surface shapes, we propose the development of a demand characterization method in which its output is in the form of a surface. By overlaying demand surfaces over Capacity iii surfaces, we are able to identify when a system meets its demands and by how much.Using the Capacity metric, computer performance optimization is evaluated against workloads in the service of individual users instead of individual applications, aggregate applications, or parallel applications. Because throughput was originally derived by drawing analogies between processor design and pipelines in the automobile industry, we introduce our Capacity metric for CHMs by drawing an analogy to automobile production, signifying that Capacity is the successor to throughput. By developing our Capacity metric, we illustrate how and why different processor organizations cannot be understood as being better performers without both magnitude and shape analysis in contrast to other metrics, such as throughput, that consider only magnitude.In this work, we make the following major ...

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Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

Cited by 76 publications

References 8 publications

Everything you always wanted to know about synchronization but were afraid to ask

Everything you always wanted to know about synchronization but were afraid to ask

Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores

Capacity metric for chip heterogeneous multiprocessors

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