Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

Abstract

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbodecoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm 2 area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm 2 /Mbps and energy efficiency of 0.55 nJ/b/iter.

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

“…All the work shown in Table III focus on the design of high performance and efficient interleavers for the 3GPP UMTS/HSPA+ turbo decoder. Among them, references [10], [11], [20], [27], [30] concentrate on the interconnection-network solving the memory conflict problem, so they did not report the area for the IAG modules. While the others present efficient solutions for IAG modules for the UMTS/HSPA+.…”

“…While for LTE mode, our implementation has better normalized area (or architecture) efficiency than most of papers listed in Table IV. Note that only [20] shows better area (or architecture) efficiency. However, it has lower energy efficiency than the proposed implementation.…”

“…(3) Runtime conflict solutions use buffers or on-chip networks to dynamically reschedule data access orders to avoid memory conflicts [11], [16], [20], [26], [27], [30], [32], [34], [36]. As discussed above, both the design-time solution and compilation-stage solution require the memory access patterns to be precomputed and stored in memory.…”

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

“…Many research papers proposed on-the-fly IAG hardware implementations [6,7,8,9,10,11]. However, most of them focused on non-parallel interleaver architectures.…”

“…Turbo codes are a class of errorcorrecting codes which are widely used in many 3G/4G communication systems due to outstanding error-correcting performance [3]. To boost the decoding throughput, many parallel turbo decoding algorithms have been investigated in the past several years [4,5,6]. As is shown in Fig.…”