Implementation of a novel LVQ neural network architecture on FPGA

Implementation of a low‐power LVQ architecture on FPGA

“…This work improves three previous research works: (i) a first work adopting the AAA [10], (ii) another sequential/parallel architecture [12] and (iii) a final LVQ parallel architecture where the authors handled serial and parallel arithmetic [13].…”

“…Nevertheless, their presented areas are only for the decision phase. Table 4 indicates and justifies the good performance of the proposed architecture, compared with [12]. The first column describes the occupied area.…”

“…A gain exceeding 28% on the occupied area is seen and 1/13 of the consumed power is noted. However, our architecture is two times and a half as slow as [12] and much slower than [10, 13] in their decision phases. Second, we compared our architecture results with the work of [26, 27].…”

“…The proposed architecture is based on an evolutionary generic architecture while predicting power consumption and low cost (power area). This architecture is compared with other implementations, as in [10, 12, 13, 26, 27]. The evaluation of the consumed power at the architectural level allows directing our architecture choice and informs us about the low‐power performance.…”

“…The achieved results for 23 inputs and 25 output neurons and with an 8‐bit input precision were 5142 slices and 69 µs at 25 MHz. In [12], the authors provided a sequential/parallel architecture where the inputs were sent in series to the neuroprocessors operating in parallel. The attained performance on the Xilinx FPGA XCV1000 were for the same topology in the decision and learning phases, as in [10] with 6852 slices and 89 µs at 25 MHz while adopting the L2 norm.…”