Implementation of a new neurochip using stochastic logic

Sato, Shusei; Nemoto, Koji; Akimoto, S.; Kinjo, Mitsunaga; Nakajima, Koji

doi:10.1109/tnn.2003.816341

Cited by 41 publications

(19 citation statements)

References 14 publications

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“…Chiju et al extends the CNN work and tests their neural model on specific applications [30]. Sato et al [31] use stochastic logic to obtain analog behavior from digital circuits. Chen and Shi [32] use pulse-width modulation.…”

Section: Neural Modelingmentioning

confidence: 99%

Biomimetic Cortical Nanocircuits

Parker

Friesz

Tseng

2009

Bio‐Inspired and Nanoscale Integrated Computing

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Section: Neural Modelingmentioning

confidence: 99%

Biomimetic Cortical Nanocircuits

Parker

Friesz

Tseng

2009

Bio‐Inspired and Nanoscale Integrated Computing

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“…When we attempt the implementation of large scale hardware neural networks, power dissipation becomes a serious problem because of the huge number of devices and interconnections required to execute the multiplication processes. Recently, a neural network using stochastic logic has been proposed to avoid the problems mentioned above [4], [5]. Stochastic neuro-chips including dozens of neurons have been realized using CMOS technology [5], [6].…”

Section: Neural Circuits Using Stochastic Logicmentioning

confidence: 99%

“…Recently, a neural network using stochastic logic has been proposed to avoid the problems mentioned above [4], [5]. Stochastic neuro-chips including dozens of neurons have been realized using CMOS technology [5], [6]. Figure 2 shows a coding method in the stochastic logic.…”

Section: Neural Circuits Using Stochastic Logicmentioning

confidence: 99%

High-speed single flux-quantum up/down counter for neural computation using stochastic logic

Onomi

Kondo

Nakajima

2008

J. Phys.: Conf. Ser.

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High-speed single flux-quantum up/down counter for neural computation using stochastic logic Abstract. We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses. IntroductionArtificial neural networks are promising for parallel and intelligent information processing. Implementation of a hardware neural network is an important subject for fields such as pattern recognition, optimization problems, and an adaptive learning. We have proposed superconducting neural circuits using stochastic logic [1]. The circuit elements have been based on a single fluxquantum(SFQ) logic[2], [3]. In the stochastic logic, the data is represented by the random pulse generation rate for a certain period on time domain. The neural computation must accumulate the pulses in order to generate the membrane potential of a neuron. We have already proposed the asynchronous up/down counter for accumulation of stochastic pulses. However, the operation speed of this counter is relatively slow(3.4GHz, 16bit) because of the slow operation in the reverse-count for the subtraction. Therefore, the operation speed of the up/down counter has limited the speed of the stochastic neuron circuit. In this paper, we propose a high-speed up/down counter for the accumulation of stochastic signals. Up and down signals are counted by two independent counters, respectively. After the signal accumulation, the final result is obtained by the subtraction between the counter of up signals and down signals. The up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. The numerical simulation shows that the up/down counter can operate at 50GHz with an enough bias margin in the accumulation phase. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method.

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“…In general, development of these systems seems to be focused towards digital systems, although there has been some work done in the analog domain [10,42]. Current neural network hardware technological advancements were more closely examined, and it was found that while there was a broad range of implementation techniques, the majority of efforts could be classified as an analog [1,9,27,2], digital [11,37,44,48,49], or hybrid (mixed-signal) [30,18,19] solution. Analog systems are preferred for large productions, very low power, very high sample rate or bandwidth, and small size.…”

Section: Existing Fuzzy and Neural Hardware Technologymentioning

confidence: 99%