Implementation of a digital trim scheme for SAR ADCs

Abstract

Abstract. Successive approximation register (SAR) analogto-digital Converters (ADC) are based on a capacitive digitalto-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

“…For applications based on multiple ADC channels working in parallel, the digital calibration of each channel leads to a very complex design. An effective solution consists of implementing a mismatch compensation technique based on an analog calibration [23][24][25] with a trimming capacitor. The spikes that usually appear in SAR converter full-range non-linearity results could be softened by applying a dynamic element matching (DEM) algorithm [26] to a partially thermometer-coded C-DAC [27].…”