Implementation of a 6.5 MHz 34-B NCO [numerically controlled oscillator]

Abstract

lNTRODUCTlONCompared to the traditional voltage controlled oscillator (CO), the numerically controlled oscillator has advantages of wide frequency tuning range, short frequency tuning time, fine frequency resolution and controlled by digital word instead of voltage that make it accurate and convenient for digital communication system.In 1971, J. Tierney first proposed the direct digital frequency synthesis schemes. The original design model was put forward by Hamil W. Cooper in 1974. The oscillator, under numeric control, generates output frequencies based on the equation below:where fo output frequency of the NCO fc accumulator clock frequency N number of bits in the accumulator K frequency control numberThe output frequency step is fc/2N. The maximum sine output frequency can approach t G fc/2 with ideal filter. After that, NCO was gradually coming into VLSl technology and the primary focus of recent work in this field has been to improve clock frequency, extend function, simplify the structure, etc. The memory scheme to reduce the. size of ROM (phase-to-amplitude converter), and the structure of pipelined accumulator or progression-of-state technique to improve the speed of accumulator was proposed in succession.To reduce the running time, a pipelined structure NCO is described in this paper. The design adopt ROM to memory the phase-amplitude covert relationship of sine wave.Considering the symmetry with the 0 and 18Gdegree axis and also the 90 and 270-degree axis, the memory volume can be decreased by a factor of four. A sense amplifier is used TO reduce the reading time. The function of phase controlling is added to determine the jhase return to zero or maintain continuity when output frequency altered, and 9-bit sine 'wave output and 10-bit phase output is provided. The maximum output frequency is iimited at fc/4 to eliminate the difficulty of filter. CHIP DESIGNThe structure of NCO is shown in Fig.1. The major factors which affect the running speed are accumulator delay and ROM reading time, the interface of the circuit provide the convenience to users. All the design issues will be discussed below: MThe circuit employed pipelinid structure and carry look-ahead chain to obtain high speed. In order to reduce redundancy of circuit and irreaularitv of interconnection. the IC 1.2 I C regular carry look ahead adder is selected. Fig.1 . Numericaly Controlled OscillatorThe pipelined accumuiator is shown in Fia.2(a), -. . the black dots represent D flip-flop groups which keep the update frequency word and provide the parallel interface. In order to cut down the cost of hardware and maintain the (0 -7803 -3062 -5)