Implementation of a 32-Bit RISC-V Processor with Cryptography Accelerators on FPGA and ASIC

Nguyen-Hoang, Duc-Thinh; Ma, Khai-Minh; Le, Duy-Linh; Thai, Hong-Hai; Cao, Tran-Bao-Thuong; Le, Duc-Hung

doi:10.1109/icce55644.2022.9852060

Cited by 9 publications

(3 citation statements)

References 3 publications

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“…Recently, some studies have focused on ASIC implementation of ModMult, ModExp, and cryptographic operation [43]- [46]. Due to the complexity of FL algorithm protocols and high cost of chip fabrication, more enterprises tend to use commercial ASIC cryptographic accelerator cards to improve computing efficiency.…”

Section: Related Workmentioning

confidence: 99%

UniFL: Accelerating Federated Learning Using Heterogeneous Hardware Under a Unified Framework

Che,

Wang,

Chen

et al. 2024

IEEE Access

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Section: Related Workmentioning

confidence: 99%

UniFL: Accelerating Federated Learning Using Heterogeneous Hardware Under a Unified Framework

Che,

Wang,

Chen

et al. 2024

IEEE Access

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“…Among many 32-bit RISC-V processor designs, designers focus on core design and emphasize document refinement to enhance understandability [2] . Implementing RISC-V processors and encryption accelerators on FPGA and ASIC has high feasibility, especially the potential in the field of hardware acceleration [3] . The flexible debugging system design for 32bit RISC-V SoC is a key factor affecting processor performance, and the debugging system is particularly important for complex on-chip systems [4] .…”

Section: Introductionmentioning

confidence: 99%

Implementing RISC-V processor with three-stage pipeline on FPGA

Zuo,

Yujie,

Wei

et al. 2024

Third International Symposium on Computer Applications and Information Systems (ISCAIS 2024)

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With the advent of the Internet of Things era, the demand for low-power, low-cost, scalable, open, and flexible chips is increasing day by day. This paper aims to design a RISC-V processor with a three-level pipeline structure, and verify its performance and functionality through verification on FPGA. The design process includes steps such as RTL design and simulation testing, RTL synthesis, constraints, Place and Route, burning, running program development and downloading, and running the built program on the RISC-V processor burned on FPGA. The kernel and peripheral design adopts a three-level pipeline design, and the functions and tasks of each stage are clearly described. The correctness and compliance of the design have been verified through waveform simulation and official testing. The design was ultimately validated on FPGA and performance analysis was conducted, indicating that the design can achieve ideal results in practical applications.

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“…However, a special place among these devices belongs to applicationspecific integrated circuits (ASICs). There are many examples presenting acceleration with dedicated integrated circuits in relation to convolutional neural networks [2], imaging technologies [3], cryptography in soft processors [4] or biomedical signal processing [5]. In this work, the authors focus mainly on biomedical data processing and medical applications.…”

Section: Introductionmentioning

confidence: 99%

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

Baryczkowski,

Szczepaniak,

Matykiewicz

et al. 2023

Electronics

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The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model.

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Implementation of a 32-Bit RISC-V Processor with Cryptography Accelerators on FPGA and ASIC

Cited by 9 publications

References 3 publications

UniFL: Accelerating Federated Learning Using Heterogeneous Hardware Under a Unified Framework

UniFL: Accelerating Federated Learning Using Heterogeneous Hardware Under a Unified Framework

Implementing RISC-V processor with three-stage pipeline on FPGA

Study of the Complexity of CMOS Neural Network Implementations Featuring Heart Rate Detection

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