Implementation in FPGA of Address-Based Data Sorting

Sklyarov, Valery; Skliarova, Iouliia; Mihhailov, Dmitri; Sudnitson, Alexander

doi:10.1109/fpl.2011.81

Cited by 24 publications

(52 citation statements)

References 9 publications

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“…For instance, the time series x = (6,8,2,4,7,3) contains four contiguous sequences with length 3, namely (6,8,2), (8,2,4), (2,4,7) and (4,7,3). The ordinal patterns for the four sequence are respectively (3, 1, 2), (2, 3, 1), (1,2,3) and (3,1,2).…”

Section: A Definition and Applicationsmentioning

confidence: 99%

“…There are papers adopting reconfigurable architectures for sorting sequences [5], [6], [7], [8]. However, these architectures are typically expensive in terms of hardware resources.…”

Section: A Sorting-free Ordinal Pattern Encodingmentioning

confidence: 99%

“…For instance, the Lehmer code of the sequence x = (3,9,5,1,7,4,8) is L(x) = (1, 5, 2, 0, 1, 0, 0). One property of this encoding scheme is that one ordinal pattern uniquely maps to a Lehmer code.…”

Section: A Sorting-free Ordinal Pattern Encodingmentioning

confidence: 99%

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Pipelined reconfigurable accelerator for ordinal pattern encoding

Guo

Luk

Weston

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Ordinal analysis is a statistical method for analysing the complexity of time series. This method has been used in characterising dynamic changes in time series, with various applications such as financial risk modelling and biomedical signal processing. Ordinal pattern encoding is a fundamental calculation in ordinal analysis. It is computationally demanding particularly for high query orders and large time series data. This paper presents the first reconfigurable accelerator for this encoding calculation, with four main contributions. First, we propose a two-level hardware-oriented ordinal pattern encoding scheme to avoid sequence sorting operations in the accelerator, enabling theoretically best code compactness. Second, we develop a hardware mapping method by promoting data reuse, by parallelising arithmetic operations, and by pipelining the data path. Third, we conduct an experimental implementation of the proposed system, showing promising accelerated performance compared to software solutions. Finally, we apply the proposed accelerator to the computation of permutation entropy, demonstrating the significant potential for acceleration that would benefit such computation.

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Section: A Definition and Applicationsmentioning

confidence: 99%

“…There are papers adopting reconfigurable architectures for sorting sequences [5], [6], [7], [8]. However, these architectures are typically expensive in terms of hardware resources.…”

Section: A Sorting-free Ordinal Pattern Encodingmentioning

confidence: 99%

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Pipelined reconfigurable accelerator for ordinal pattern encoding

Guo

Luk

Weston

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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“…While method [22] is obviously simple and effective, there are still some significant performance flaws associated with it. For example, if we sort M-bit data, then quite often the number of input data items Q is significantly less than 2 M (Q<<2 M ).…”

Section: Introductionmentioning

confidence: 98%

“…A simple but efficient sorting technique, which is fairly unique to FPGA, called address-based sorting was proposed in [22]. The main idea is rather simple.…”

Section: Introductionmentioning

confidence: 99%

Address-based data processing over N-ary trees

et al. 2013

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The existing trends and growing tendency to high-performance computing strongly require traditional computational algorithms to be revised in such a way that would permit optimal hardware implementations to be found. The latter can be done if algorithms can efficiently be mapped to hardware-specific functional blocks that require different style of thinking and manipulation by different operations and memory models. Besides, concurrency (pipelining and parallelism) can be widely applied. This paper focuses on data processing algorithms that use values of incoming data items as memory addresses with one-bit flags indicating presence or absence of data. The main problem of similar known methods is an appearance of huge number of memory cells with no data items (empty holes), which, nevertheless, have to be processed involving lots of unnecessary time. It is proposed to apply N-ary tree technique that enables data items to be stored and found very fast through executing special traversal procedure. Such trees completely differ from known tree-walk tables because they have pre-established configuration that does not require explicit addresses of subsequent (child) nodes. As a result the size of memory needed to keep data items is decreased in number of times. Finally, significantly more complicated problems can be solved faster and with smaller hardware resources. The presented results of numerous experiments clearly demonstrate advantages of the proposed method compared to known implementations.

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High-Performance Data Processing Over N-ary Trees

Sklyarov

Skliarova

2013

High-Performance Computing Using FPGAs

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Implementation in FPGA of Address-Based Data Sorting

Cited by 24 publications

References 9 publications

Pipelined reconfigurable accelerator for ordinal pattern encoding

Pipelined reconfigurable accelerator for ordinal pattern encoding

Address-based data processing over N-ary trees

High-Performance Data Processing Over N-ary Trees

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